Jason Yeung

Data Mining for Diverse E-Commerce Applications

Amar Gupta, Sanjeev Vadhavkar, Jason Yeung, 2002 .

A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency

Jae Choi, Ming Liu, Ben Lee, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

Mahmudul Hassan, Khaldoon Abugharbieh, Chethan Rao, 2014 .

A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

Chethan Rao, Prashant Choudhary, Paul Jennings, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

Automated Design Data and Rationale Capture

Tara N. Sainath, Amar Gupta, Satwik Seshasai, 2002 .