Jam-Wem Lee

A new MOSFET hot carrier model in SPICE feasible for VLSI reliability analysis

Steve S. Chung, P.-C. Hsu, Jam-Wem Lee, 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.

5nm-gate nanowire FinFET

Chenming Hu, Yee-Chia Yeo, Mong-Song Liang, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

Shao-Ming Yu, Yiming Li, Jam-Wem Lee, 2005 .

Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Jam-Wem Lee, Po-Hao Lee, Shen-De Wang, 2006, IEEE Transactions on Electron Devices.

Optimization of the anti-punch-through implant for electrostatic discharge protection circuit design

Yiming Li, Jam-Wem Lee, S. M. Sze, 2003 .

A new approach to determine the drain-and-source series resistance of LDD MOSFET's

Steve S. Chung, Jam-Wem Lee, S. Chung, 1993 .

Impacts of process options on ESD device characteristics in sub-20nm bulk FinFET technology nodes

Mirko Scholz, Dimitri Linten, Geert Hellings, 2014 .

A robust design for fully-silicided electrostatic discharge protection devices in sub-100 nm CMOS circuit era

Yiming Li, Jam-Wem Lee, 2003, 2003 Third IEEE Conference on Nanotechnology, 2003. IEEE-NANO 2003..