S. Burc Eryilmaz

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models

Gert Cauwenberghs, Wenqiang Zhang, Weier Wan, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

Jan M. Rabaey, H.-S. Philip Wong, Mohamed M. Sabry, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Capacity optimization of emerging memory systems: A shannon-inspired approach to device characterization

Chung Lam, Bruno A. Olshausen, S. Burc Eryilmaz, 2014, 2014 IEEE International Electron Devices Meeting.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

S. Burc Eryilmaz, Min-Cheng Chen, Jia-Min Shieh, 2016, 2016 IEEE Symposium on VLSI Technology.

Author Correction: Analog Coding in Emerging Memory Systems

Chung Lam, Bruno A. Olshausen, Weier Wan, 2020, Scientific Reports.