Eric Qin

SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training

Dipankar Das, Hyoukjun Kwon, Tushar Krishna, 2020, 2020 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

Sung Kyu Lim, Madhavan Swaminathan, Gauthaman Murali, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Context-aware control of smart objects via human-machine communication

Ümit Y. Ogras, Nicholas Tran, Md Muztoba, 2015, 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS).

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU

Christopher J. Hughes, Hyesoon Kim, Tushar Krishna, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

A Taxonomy for Classification and Comparison of Dataflows for GNN Accelerators pdf

Eduard Alarcón, Sivasankaran Rajamanickam, José L. Abellán, 2021, ArXiv.

Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems

Sung Kyu Lim, Madhavan Swaminathan, Tushar Krishna, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity

Sivasankaran Rajamanickam, Tushar Krishna, Cong Hao, 2022, ArXiv.

Understanding the Design Space of Sparse/Dense Multiphase Dataflows for Mapping Graph Neural Networks on Spatial Accelerators.

Sivasankaran Rajamanickam, Manuel E. Acacio, Tushar Krishna, 2021 .

Extending Sparse Tensor Accelerators to Support Multiple Compression Formats

Dipankar Das, Sheng-Chun Kao, Sivasankaran Rajamanickam, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS).