A. Boudaoud

VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate

E. Abdelmounim, A. Boudaoud, M. El Haroussi, 2017 .

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes

E. Abdelmounim, A. Boudaoud, M. El Haroussi, 2017 .