M. El Haroussi

VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate

E. Abdelmounim, A. Boudaoud, M. El Haroussi, 2017 .

VHDL design and FPGA implementation of a fully parallel BCH SISO decoder

M. El Haroussi, I. Chana, M. Belkasmi, 2010, 2010 5th International Symposium On I/V Communications and Mobile Network.

VHDL Design and FPGA Implementation of a Fully Parallel Architecture for Iterative Decoder of Majority Logic Codes for High Data Rate Applications

Mostafa Belkasmi, M. El Haroussi, M. Belkasmi, 2012 .

VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes

E. Abdelmounim, A. Boudaoud, M. El Haroussi, 2017 .

VHDL design and FPGA implementation of weighted majority logic decoders

F. Ayoub, M. El Haroussi, M. Belkasmi, 2011, 2011 International Conference on Multimedia Computing and Systems.