C. K. Teh

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology

Chen Kong Teh, F. Yamane, M. Hamada, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer

Makoto Arai, Hiroyuki Kobayashi, Atsushi Suzuki, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS

Mototsugu Hamada, Chen Kong Teh, Hiroyuki Hara, 2011, 2011 IEEE International Solid-State Circuits Conference.

Inductance calculation of 3D superconducting structures with ground plane

Y. Okabe, M. Kitagawa, C. K. Teh, 1999 .