Ranga Vemuri

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A VHDL-AMS compiler and architecture generator for behavioral synthesis of analog systems

Alex Doboli, Ranga Vemuri, R. Vemuri, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms

Ranga Vemuri, Jawad Khan, Balasubramanian Sethuraman, 2004, ERSA.

Simultaneous scheduling, binding and layer assignment for synthesis of vertically integrated 3D systems

Ranga Vemuri, Madhubanti Mukherjee, R. Vemuri, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

Constraint allocation in analog system synthesis

Ranga Vemuri, Nagu R. Dhanwada, R. Vemuri, 1998, Proceedings Eleventh International Conference on VLSI Design.

Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits

Ranga Vemuri, Hao Xu, Venkat Krishnan Balasubramanian, 2013, 2013 IEEE International SOC Conference.

Task-level partitioning and RTL design space exploration for multi-FPGA architectures

Ranga Vemuri, Vinoo Srinivasan, 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

Algorithms for topology synthesis of analog circuits

Ranga Vemuri, Angan Das, 2008 .

An integrated temporal partitioning and partial reconfiguration technique for design latency improvement

Ranga Vemuri, S. Ganesan, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

Formal verification of synthesized analog designs

Ranga Vemuri, Abhijit Ghosh, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Dynamic virtual ground voltage estimation for power gating

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2008, Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08).

Abstract models of reconfigurable architectures for synthesis and compilation

Ranga Vemuri, Jeff Walrath, 1998, Other Conferences.

Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2008, 2008 IEEE International Conference on Computer Design.

Fast evaluation of digital switching noise for synthesis of mixed-signal applications

Alex Doboli, Ranga Vemuri, 2001, Proceedings of the Fifth IEEE International Workshop on Behavioral Modeling and Simulation. BMAS 2001 (Cat No.01TH8601).

Online placement and scheduling algorithms and methodologies for reconfigurable computing systems

Ranga Vemuri, Manish Handa, 2004 .

A unified specification model of concurrency and coordination for synthesis from VHDL

Ranga Vemuri, Vinoo Srinivasan, Iyad Ouaiss, 2017 .

DSS: a distributed high-level synthesis system

Ranga Vemuri, Rajiv Dutta, Nand Kumar, 1992, IEEE Design & Test of Computers.

Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits

Ranga Vemuri, Almitra Pradhan, R. Vemuri, 2009, 2009 22nd International Conference on VLSI Design.

Rapid prototyping of reconfigurable coprocessors

Ranga Vemuri, Vinoo Srinivasan, Sriram Govindarajan, 1996, Proceedings of International Conference on Application Specific Systems, Architectures and Processors: ASAP '96.

Configurable Computing: Technology and Applications - Guest Editors' Introduction

Ranga Vemuri, Randolph E. Harr, 2000, Computer.

A Design Methodology for Self-Timed Event Logic Pipelines

Ranga Vemuri, Xin Jia, 2004, ESA/VLSI.

Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Hierarchical scheduling in high level synthesis using resource sharing across nested loops

Ranga Vemuri, Abhijit Ghosh, Sandeep K. Lodha, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Forward-looking macro generation and relational placement during high level synthesis to FPGAs

Ranga Vemuri, Renqiu Huang, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

A spline based regression technique on interval valued noisy data

Ranga Vemuri, Balaji Kommineni, Shubhankar Basu, 2007, Sixth International Conference on Machine Learning and Applications (ICMLA 2007).

Reconfigurable Multicore Architecture for Dynamic Processor Reallocation

Ranga Vemuri, Annie Avakian, Natwar Agrawal, 2012, ARC.

Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs

Ranga Vemuri, Meenakshi Kaul, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Optimal and near-optimal temporal partitioning techniques for reconfigurable computers

Ranga Vemuri, Meenakshi Kaul, 2000 .

Accurate energy breakeven time estimation for run-time power gating

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2008, ICCAD 2008.

The Waves Dataset

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Hardware assisted two dimensional ultra fast online placement

Ranga Vemuri, Manish Handa, 2005, Int. J. Embed. Syst..

Efficient Temperature - Dependent Symbolic Sensitivity Analysis and Symbolic Performance Evaluation in Analog Circuit Synthesis

Ranga Vemuri, Huiying Yang, 2006, Proceedings of the Design Automation & Test in Europe Conference.

MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).

Performance verification using PDL and constraint satisfaction

Ranga Vemuri, W. L. Bradley, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Automated layout-inclusive synthesis of analog circuits using symbolic performance models

Ranga Vemuri, Mukesh Ranjan, R. Vemuri, 2005 .

Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS

Alex Doboli, Ranga Vemuri, R. Vemuri, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method

Ranga Vemuri, Suyuan Chen, 2018, ACM Great Lakes Symposium on VLSI.

An Integrated Online Scheduling and Placement Methodology

Ranga Vemuri, Manish Handa, 2004, FPL.

Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs

Ranga Vemuri, Nazanin Mansouri, R. Vemuri, 2000, Formal Methods Syst. Des..

Exact hierarchical symbolic analysis of large analog networks using a general interconnection template

Ranga Vemuri, Mukesh Ranjan, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples

Ranga Vemuri, Balaji Kommineni, Shubhankar Basu, 2008, 21st International Conference on VLSI Design (VLSID 2008).

An iterative algorithm for partitioning and scheduling of area constrained HW-SW systems

Ranga Vemuri, Karam S. Chatha, 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications

Ranga Vemuri, Jawad Khan, Manish Handa, 2002, FPL.

Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines

Ranga Vemuri, Glenn Wolfe, R. Vemuri, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits

Ranga Vemuri, Glenn Wolfe, Anuradha Agarwal, 2005, GLSVLSI '05.

GAPLA: A Asynchronous Locally Synchronous FPGA Architecture

Ranga Vemuri, Xin Jia, 2005 .

Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits

Ranga Vemuri, Suyuan Chen, 2019, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS

Ranga Vemuri, Sriram Govindarajan, R. Vemuri, 2000, FPL.

Multicomponent Synthesis for Multichip Modules (MCMs)

Ranga Vemuri, 2001 .

An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

Ranga Vemuri, Iyad Ouaiss, Sriram Govindarajan, 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

Hardware-software partitioning and pipelined scheduling of transformative applications

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 2002, IEEE Trans. Very Large Scale Integr. Syst..

A fast macro based compilation methodology for partially reconfigurable FPGA designs

Ranga Vemuri, Madhubanti Mukherjee, Manish Handa, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

Hierarchical behavioral partitioning for multicomponent synthesis

Ranga Vemuri, Vinoo Srinivasan, Nand Kumar, 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability

Ranga Vemuri, Richa Agrawal, Harsh Vamja, 2019, 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS).

Adaptive performance modeling of reconfigurable vlsi systems

Ranga Vemuri, Jeffrey Walrath, 1999 .

Analysis and evaluation of a hybrid interconnect structure for FPGAs

Ranga Vemuri, R. Huang, 2004, ICCAD 2004.

Accounting for various register allocation schemes during post-synthesis verification of RTL designs

Ranga Vemuri, Nazanin Mansouri, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Synchronous controller models for synthesis from communicating VHDL processes

Ranga Vemuri, Naren Narasimhan, Jay Roy, 1996, Proceedings of 9th International Conference on VLSI Design.

Performance evaluation tool for rapid prototyping of hardware-software codesigns

Ranga Vemuri, Karam S. Chatha, 1998, Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237).

Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures

Ranga Vemuri, Vinoo Srinivasan, Jeffrey Walrath, 1999, IPPS/SPDP Workshops.

Partitioning for fpga-based reconfigurable computers

Ranga Vemuri, Vinoo Srinivasan, 1999 .

A search and retrieval tool to enable system design through intellectual property reuse

Ranga Vemuri, Perry Alexander, P. Chawla, 1998, Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185).

Combined temporal partitioning and scheduling for reconfigurable architectures

Ranga Vemuri, Awartika Pandey, R. Vemuri, 1999, Optics East.

An Automated Passive Analog Circuit Synthesis Framework using Genetic Algorithms

Ranga Vemuri, Angan Das, R. Vemuri, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Architectural synthesis techniques for design of correct and secure ics

Ranga Vemuri, V. Sundaresan, 2008 .

Transformation synthesis for data intensive applications to FPGAs

Ranga Vemuri, Renqiu Huang, 2006, GLSVLSI '06.

Global memory mapping for FPGA-based reconfigurable systems

Ranga Vemuri, Iyad Ouaiss, R. Vemuri, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Validation of Synthesized Register-Transfer Level Designs Using Simulation and Formal Verification

Ranga Vemuri, R. Kalyanaraman, N. Narasimhan, 1996 .

Fast Heuristics for Near-Optimal Signal Restoration in Post-Silicon Validation

Ranga Vemuri, Xiaobang Liu, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Hierarchical performance optimization for synthesis of linear analog systems

Alex Doboli, Ranga Vemuri, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

A technique for dynamic high-level exploration during behavioral-partitioning for multi-device architectures

Ranga Vemuri, Vinoo Srinivasan, Preetham Lakshmikanthan, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Hierarchical constraint transformation using directed interval search for analog system synthesis

Ranga Vemuri, Adrián Núñez-Aldana, Nagu R. Dhanwada, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Behavioral synthesis of analog systems using two-layered design space exploration

Alex Doboli, Ranga Vemuri, Adrián Núñez-Aldana, 1999, DAC '99.

An effective design system for dynamically reconfigurable architectures

Ranga Vemuri, Vinoo Srinivasan, Iyad Ouaiss, 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

Accurate resource estimation algorithms for behavioral synthesis

Ranga Vemuri, Srinivas Katkoori, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool

Ranga Vemuri, Nazanin Mansouri, 1998, FMCAD.

Analysis and evaluation of a hybrid interconnect structure for FPGAs

Ranga Vemuri, Renqiu Huang, 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

On SAT-Based Attacks On Encrypted Sequential Logic Circuits

Ranga Vemuri, Suyuan Chen, Yasaswy Kasarabada, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

The Definition of a VHDL-AMS Subset for Behavioral Synthesis of Analog Systems

Alex Doboli, Ranga Vemuri, R. Vemuri, 1998 .

An integrated multicomponent synthesis environment for MCMs

Ranga Vemuri, Ning Ren, Nand Kumar, 1993, Computer.

The History and Background of Waves

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Behavioral partitioning in the synthesis of mixed analog-digital systems

Ranga Vemuri, Sree Ganesan, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Fast and accurate parasitic capacitance models for layout-aware synthesis of analog circuits

Ranga Vemuri, Hemanth Sampath, Anuradha Agarwal, 2004, Proceedings. 41st Design Automation Conference, 2004..

A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis

Ranga Vemuri, Adrián Núñez-Aldana, Nagu R. Dhanwada, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

Interactive Waveforms: Handshaking and Matching

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Simulation based architectural power estimation for PLA-based controllers

Ranga Vemuri, Srinivas Katkoori, 1996, ISLPED.

SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits

Ranga Vemuri, Mike Borowczak, Lakshmi Narasimhan Ramakrishnan, 2012, 2012 IEEE International Symposium on Hardware-Oriented Security and Trust.

Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques

Ranga Vemuri, Shubhankar Basu, Priyanka Thakore, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance

Ranga Vemuri, S. Basu, B. Kommineni, 2008, ISQED 2008.

Trust in IoT Devices: A Logic Encryption Perspective

Ranga Vemuri, David Luria, Yasaswy Kasarabada, 2019, IFIPIoT.

Energy management in battery-powered sensor networks with reconfigurable computing nodes

Ranga Vemuri, Jawad Khan, 2005, International Conference on Field Programmable Logic and Applications, 2005..

A State Machine Encoding Methodology Against Power Analysis Attacks

Ranga Vemuri, Richa Agrawal, Mike Borowczak, 2019, J. Electron. Test..

Physical aware high level synthesis and interconnect for fpgas

Ranga Vemuri, Renqiu Huang, 2006 .

Using GALS architecture to reduce the impact of long wire delay on FPGA performance

Ranga Vemuri, Xin Jia, 2005, ASP-DAC.

An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels

Ranga Vemuri, Glenn Wolfe, Mengmeng Ding, 2005, ASP-DAC.

A Portable Face Recognition System Using Reconfigurable Hardware

Ranga Vemuri, Jawad Khan, Renqiu Huang, 2004, ERSA.

Distributed design-space exploration for high-level synthesis systems

Ranga Vemuri, Rajiv Dutta, Jayanta Roy, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

Multicasting based topology generation and core mapping for a power efficient networks-on-chip

Ranga Vemuri, Balasubramanian Sethuraman, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems

Ranga Vemuri, Meenakshi Kaul, R. Vemuri, 2000, J. VLSI Signal Process..

Hardware-Software Codesign for Dynamically Reconfigurable Architectures

Ranga Vemuri, Karam S. Chatha, 1999, FPL.

A spline based regression technique on interval valued noisy data

Ranga Vemuri, S. Basu, B. Kommineni, 2007, ICMLA 2007.

Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs

Ranga Vemuri, Shubhankar Basu, 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

Genetic algorithm for MCM partitioning

Ranga Vemuri, R. Vemuri, 1994 .

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams

Ranga Vemuri, Georges G. E. Gielen, Huiying Yang, 2005, ASP-DAC.

optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs

Ranga Vemuri, Balasubramanian Sethuraman, 2006, Proceedings of the Design Automation & Test in Europe Conference.

On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System

Ranga Vemuri, Naren Narasimhan, R. Vemuri, 1998, TPHOLs.

PAHLS: towards run-time synthesis for FPGAs

Ranga Vemuri, Renqiu Huang, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs

Ranga Vemuri, Manish Handa, Renqiu Huang, 2004, FPL.

Accurate energy breakeven time estimation for run-time power gating

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

Dynamic bounding of successor force computations in the force directed list scheduling algorithm

Ranga Vemuri, Sriram Govindarajan, R. Vemuri, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

An analog performance estimator for improving the effectiveness of CMOS analog systems circuit synthesis

Ranga Vemuri, Adrián Núñez-Aldana, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

Computer Aided Engineering for Reconfigurable Computing (CAERC)

Ranga Vemuri, 2001 .

Capturing Waveforms and Supporting Automatic Test Equipment (ATE)

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

A prediction-based, data Migration Algorithm for hybrid Architecture NoC systems

Ranga Vemuri, Annie Avakian, Jon Nafziger, 2010, 23rd IEEE International SOC Conference.

Programmed Monitoring and Digital System Simulation

Ranga Vemuri, Peter J. Ashenden, Philip A. Wilsey, 1997 .

A regularity-based hierarchical symbolic analysis method for large-scale analog networks

Ranga Vemuri, Alex Doboli, R. Vemuri, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

An active learning scheme using support vector machines for analog circuit feasibility classification

Ranga Vemuri, Mengmeng Ding, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Architectural Power Estimation Based on Behavior Level Profiling

Ranga Vemuri, Srinivas Katkoori, R. Vemuri, 1998, VLSI Design.

Performance Modeling Using PDL

Ranga Vemuri, Ram Manday, Vijay Meduri, 1996, Computer.

Cone-based clustering heuristic for list-scheduling algorithms

Ranga Vemuri, Sriram Govindarajan, R. Vemuri, 1997, Proceedings European Design and Test Conference. ED & TC 97.

MCM layer assignment using genetic search

Ranga Vemuri, R. Vemuri, 1994 .

Enabling Side Channel Secure FSMs in the Presence of Low Power Requirements

Ranga Vemuri, Mike Borowczak, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Power invariant secure IC design methodology using reduced complementary dynamic and differential logic

Ranga Vemuri, Vijay Sundaresan, Srividhya Rammohan, 2007, VLSI-SoC.

CAD tools for a globally asynchronous locally synchronous FPGA architecture

Ranga Vemuri, Xin Jia, R. Vemuri, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2010, 2010 23rd International Conference on VLSI Design.

Power variations of multi-port routers in an application-specific NoC design : A case study

Ranga Vemuri, Balasubramanian Sethuraman, 2007, 2007 25th International Conference on Computer Design.

Dynamic Characteristics of Power Gating During Mode Transition

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Accurate estimation of parasitic capacitances in analog circuits

Ranga Vemuri, Hemanth Sampath, Anuradha Agarwal, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Analog VLSI circuit-level synthesis using multi-placement structures

Ranga Vemuri, Raoul F. Badaoui, R. Vemuri, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Performance Specification Using Attributed Grammars

Ranga Vemuri, Ram Mandayam, R. Vemuri, 1993, 30th ACM/IEEE Design Automation Conference.

An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms

Ranga Vemuri, Jawad Khan, R. Vemuri, 2004, FPL.

Temporal and spatial idleness exploitation for optimal-grained leakage control

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs

Ranga Vemuri, Ramesh Nair, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation

Ranga Vemuri, Xiaobang Liu, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Temporal Precondition Verification of Design Transformations

Ranga Vemuri, Anuradha Sridhar, 1991, CAV.

Guest editorial reconfigurable and adaptive VLSI systems

Ranga Vemuri, Rajesh K. Gupta, 2001, IEEE Trans. Very Large Scale Integr. Syst..

Specification of Control Flow Properties for Verification of Synthesized VHDL Designs

Ranga Vemuri, Naren Narasimhan, 1996, FMCAD.

Library finding for high-level synthesis of analog systems

Ranga Vemuri, Sree Ganesan, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection

Ranga Vemuri, Almitra Pradhan, R. Vemuri, 2008, GLSVLSI '08.

Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures

Ranga Vemuri, Meenakshi Kaul, R. Vemuri, 1999, IPPS/SPDP Workshops.

Algorithms for layout-aware and performance model driven synthesis of analog circuits

Ranga Vemuri, Anuradha Agarwal, R. Vemuri, 2005 .

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis

Ranga Vemuri, Sriram Govindarajan, Rajesh Radhakrishnan, 2001, Formal Methods Syst. Des..

Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams

Ranga Vemuri, Huiying Yang, Anuradha Agarwal, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Framework for synthesis of virtual pipelines

Ranga Vemuri, Rajesh Radhakrishnan, Srinivasan Dasasathyan, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Automatic data path abstraction for verification of large scale designs

Ranga Vemuri, Nazanin Mansouri, Viresh Paruthi, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

A profile driven approach for low power synthesis

Ranga Vemuri, Srinivas Katkoori, N. Kumar, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design

Ranga Vemuri, Angan Das, 2009, 2009 22nd International Conference on VLSI Design.

Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints

Ranga Vemuri, Vinoo Srinivasan, Preetham Lakshmikanthan, 2000, IPDPS Workshops.

Efficient resource arbitration in reconfigurable computing environments

Ranga Vemuri, Iyad Ouaiss, 2000, DATE '00.

Integrated high-level synthesis and power-net routing for digital design under switching noise constraints

Alex Doboli, Ranga Vemuri, 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

Experiences in Functional Validation of a High Level Synthesis System

Ranga Vemuri, Nand Kumar, Jayanta Roy, 1993, 30th ACM/IEEE Design Automation Conference.

Tuning Vth Hopping for Aggressive Runtime Leakage Control

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2010, J. Low Power Electron..

Progressive and secure performance unlocking for digital integrated circuits

Ranga Vemuri, Renuka Lokare, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

for Hybrid Architecture Noe Systems

Ranga Vemuri, Annie Avakian, Jon Nafziger, 2010 .

A tool for partitioning and pipelined scheduling of hardware-software systems

Ranga Vemuri, Karam S. Chatha, 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).

A novel synthesis strategy driven by partial evaluation based circuit reduction for application specific DSP circuits

Ranga Vemuri, M. Mukherjee, R. Vemuri, 2003, Proceedings 21st International Conference on Computer Design.

Performance estimation for analog and mixed-signal synthesis

Ranga Vemuri, Adrian Nunez-Aldana, 2000 .

A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications

Alex Doboli, Ranga Vemuri, 1999, VLSI.

Moment-driven coupling-aware routing methodology

Ranga Vemuri, Amitava Bhaduri, R. Vemuri, 2005, ACM Great Lakes Symposium on VLSI.

A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications

Alex Doboli, Ranga Vemuri, Adrián Núñez-Aldana, 2004, TODE.

A NOVEL ASYNCHRONOUS FPGA ARCHITECTURE DESIGN AND ITS PERFORMANCE EVALUATION

Ranga Vemuri, Xin Jia, R. Vemuri, 2000 .

A secure tunable-precision architecture for image processing applications

Ranga Vemuri, Ankita Manjunath Nayak, R. Vemuri, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

An approach to high-level synthesis system validation using formally verified transformations

Ranga Vemuri, Rajesh Radhakrishnan, Elena Teica, 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).

Automated design synthesis and partitioning for adaptive reconfigurable hardware

Ranga Vemuri, Vinoo Srinivasan, Preetham Lakshmikanthan, 2001 .

An efficient algorithm for finding empty space for online FPGA placement

Ranga Vemuri, Manish Handa, R. Vemuri, 2004, Proceedings. 41st Design Automation Conference, 2004..

Improving the schedule quality of static-list time-constrained scheduling (poster paper)

Ranga Vemuri, Sriram Govindarajan, 2000, DATE '00.

On the Effectiveness of the Satisfiability Attack on Split Manufactured Circuits

Ranga Vemuri, Suyuan Chen, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

Ranga Vemuri, Karam S. Chatha, 2000, Des. Autom. Embed. Syst..

Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits

Ranga Vemuri, Anuradha Agarwal, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Continuous wavelet transform on reconfigurable meshes

Yi Pan, Ranga Vemuri, Jie Li, 2001, Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001.

Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches

Ranga Vemuri, Almitra Pradhan, 2008, 2008 Design, Automation and Test in Europe.

Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis

Ranga Vemuri, Almitra Pradhan, 2007, VLSI-SoC.

A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems

Ranga Vemuri, Nagu R. Dhanwada, A. Doboli, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Technology mapping and retargeting for field-programmable analog arrays

Ranga Vemuri, Sree Ganesan, 2000, DATE '00.

Symbolic time-domain behavioral and performance modeling of linear analog circuits using an efficient symbolic Newton-iteration algorithm for pole extraction

Ranga Vemuri, Ritochit Chakraborty, Mukesh Ranjan, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

A combined feasibility and performance macromodel for analog circuits

Ranga Vemuri, Mengmeng Ding, 2005, Proceedings. 42nd Design Automation Conference, 2005..

A novel approach to performance-oriented datapath allocation and floorplanning

Ranga Vemuri, Vijay Sundaresan, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Simulation based architectural power estimation for PLA-based controllers

Ranga Vemuri, Srinivas Katkoori, R. Vemuri, 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking

Ranga Vemuri, Suyuan Chen, 2018, 2018 IEEE 36th International Conference on Computer Design (ICCD).

A novel simulation based approach for trace signal selection in silicon debug

Ranga Vemuri, Prabanjan Komari, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications

Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, 2002, TODE.

An integrated temporal partioning and partial reconfiguration technique for design latency improvement

Ranga Vemuri, Satish Ganesan, 2000, DATE '00.

Efficient analog performance macromodeling via sequential design space decomposition

Ranga Vemuri, Mengmeng Ding, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space

Ranga Vemuri, Balaji Kommineni, Shubhankar Basu, 2009, 2009 22nd International Conference on VLSI Design.

Inductive and capacitive coupling aware routing methodology driven by a higher order RLCK moment metric

Ranga Vemuri, Amitava Bhaduri, 2005, Design, Automation and Test in Europe.

Continuing education in microprocessors: Use of software simulators

Ranga Vemuri, J. V. Cornacchio, 1978, COMPSAC.

FAAR: A router for field-programmable analog arrays

Ranga Vemuri, Sree Ganesan, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

FPGA/FPAA-based rapid prototyping environment for mixed signal systems

Ranga Vemuri, Sreelakshmi P. Ganesan, 1999, Optics East.

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers

Ranga Vemuri, Iyad Ouaiss, R. Vemuri, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A Performance Modeling and Analysis Environment for Reconfigurable Computers

Ranga Vemuri, Jeffrey Walrath, R. Vemuri, 1998, IPPS/SPDP Workshops.

The External File

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Formal verification of synthesized mixed signal designs using *BMDs

Ranga Vemuri, Abhijit Ghosh, 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

Effective Signal Restoration in Post-Silicon Validation

Ranga Vemuri, Xiaobang Liu, 2017, 2017 IEEE International Conference on Computer Design (ICCD).

Scheduling for low power under resource and latency constraints

Ranga Vemuri, Srinivas Katkoori, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Multi-placement structures for fast and optimized placement in analog circuit synthesis

Ranga Vemuri, Raoul F. Badaoui, R. Vemuri, 2005, Design, Automation and Test in Europe.

Detection of Sequential Trojans in Embedded System Designs Without Scan Chains

Ranga Vemuri, Pranav Dharmadhikari, Akhilesh Raju, 2018, 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

A fast algorithm for finding maximal empty rectangles for dynamic FPGA placement

Ranga Vemuri, Manish Handa, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

A reconfigurable architecture for multicore systems

Ranga Vemuri, Annie Avakian, Amayika Panda, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

High level profiling based low power synthesis technique

Ranga Vemuri, Srinivas Katkoori, Nand Kumar, 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

Some Practical Issues and Examples in Waves

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Topology synthesis of analog circuits based on adaptively generated building blocks

Ranga Vemuri, Angan Das, 2008, 2008 45th ACM/IEEE Design Automation Conference.

An Automated Temporal Partitioning Tool for a class of DSP applications

Ranga Vemuri, Meenakshi Kaul, 1998, PACT 1998.

Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip

Ranga Vemuri, Balasubramanian Sethuraman, 2006, 2006 International Conference on Field Programmable Logic and Applications.

A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements

Ranga Vemuri, Adrián Núñez-Aldana, 1999, VLSI.

Application specific macro based synthesis

Ranga Vemuri, Sriram Govindarajan, Sujatha Sundararaman, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

A graph grammar based approach to automated multi-objective analog circuit design

Ranga Vemuri, Angan Das, R. Vemuri, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

StateLock: State Transition Based Logic Locking for Sequential Circuits

Ranga Vemuri, Yasaswy Kasarabada, 2020, 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID).

Rapidly porting commercial electronic designs to radiation-hardened domain

Ranga Vemuri, Maya Rubeiz, Johan Sandstrom, 2001 .

Hardware assisted two dimensional ultra fast placement

Ranga Vemuri, Manish Handa, 2004, 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings..

Layout-aware RF circuit synthesis driven by worst case parasitic corners

Ranga Vemuri, Anuradha Agarwal, R. Vemuri, 2005, 2005 International Conference on Computer Design.

Algorithms for design space exploration and high-level synthesis for multi-fpga reconfigurable computers

Ranga Vemuri, Sriram Govindarajan, 2000 .

A Self-learning Optimization Technique for Topology Design of Computer Networks

Ranga Vemuri, Angan Das, 2008, EvoWorkshops.

Component characterization and constraint transformation based on directed intervals for analog synthesis

Ranga Vemuri, Adrián Núñez-Aldana, Nagu R. Dhanwada, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures

Ranga Vemuri, Vinoo Srinivasan, 1999, FPGA.

A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures

Ranga Vemuri, Balasubramanian Sethuraman, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Energy management for battery-powered reconfigurable computing platforms

Ranga Vemuri, Jawad Khan, R. Vemuri, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

LiPaR: A light-weight parallel router for FPGA-based networks-on-chip

Ranga Vemuri, Jawad Khan, Balasubramanian Sethuraman, 2005, ACM Great Lakes Symposium on VLSI.

A functional specification notation for co-design of mixed analog-digital systems

Alex Doboli, Ranga Vemuri, R. Vemuri, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Signal Selection Heuristics for Post-Silicon Validation

Ranga Vemuri, Suprajaa Tummala, Xiaobang Liu, 2020, 2020 21st International Symposium on Quality Electronic Design (ISQED).

Optimal temporal partitioning and synthesis for reconfigurable architectures

Ranga Vemuri, Meenakshi Kaul, 1998, Proceedings Design, Automation and Test in Europe.

Memory Synthesis for FPGA-Based Reconfigurable Computers

Ranga Vemuri, Iyad Ouaiss, Amit Kasat, 2001, FPL.

A constructive method for data path area estimation during high-level VLSI synthesis

Dinesh Bhatia, Ranga Vemuri, Anurag Gupta, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

A high level language for pre-layout extraction in parasite-aware analog circuit synthesis

Ranga Vemuri, Hemanth Sampath, Anuradha Agarwal, 2004, GLSVLSI '04.

Verification of Basic Block Schedules Using RTL Transformations

Ranga Vemuri, Rajesh Radhakrishnan, Elena Teica, 2001, CHARME.

Specification and design-space exploration for high-level synthesis of analog and mixed-signal systems

Ranga Vemuri, Alexa Doboli, 2000 .

On the notion of the normal form register-level structures and its applications in design-space exploration

Ranga Vemuri, 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

Battery-efficient task execution on reconfigurable computing platforms with multiple processing units

Ranga Vemuri, Jawad Khan, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

Variation Aware Spline Center and Range Modeling for Analog Circuit Performance

Ranga Vemuri, Balaji Kommineni, Shubhankar Basu, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models

Ranga Vemuri, Georges G. E. Gielen, Hemanth Sampath, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Parasitic aware routing methodology based on higher order RLCK moment metrics

Ranga Vemuri, Amitava Bhaduri, R. Vemuri, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Extraction and use of neural network models in automated synthesis of operational amplifiers

Ranga Vemuri, Glenn Wolfe, R. Vemuri, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Regression based circuit matrix models for accurate performance estimation of analog circuits

Ranga Vemuri, Almitra Pradhan, 2007, 2007 IFIP International Conference on Very Large Scale Integration.

Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures

Ranga Vemuri, V. Srinivasan, Sriram Govindarajan, 2001, IEEE Trans. Very Large Scale Integr. Syst..

A Dynamically Reconfigurable Asynchronous FPGA Architecture

Ranga Vemuri, Xin Jia, Jayanthi Rajagopalan, 2004, FPL.

Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis

Ranga Vemuri, Sriram Govindarajan, Rajesh Radhakrishnan, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Battery-efficient task execution on portable reconfigurable computing

Ranga Vemuri, Jawad Khan, Balasubramanian Sethuraman, 2004, IEEE International SOC Conference, 2004. Proceedings..

Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies

Alex Doboli, Ranga Vemuri, R. Vemuri, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Radu Marculescu, Majid Sarrafzadeh, Vishwani D. Agrawal, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures

Ranga Vemuri, Vinoo Srinivasan, Iyad Ouaiss, 1998, IPPS/SPDP Workshops.

Studying a GALS FPGA Architecture Using a Parameterized Automatic Design Flow

Ranga Vemuri, Xin Jia, R. Vemuri, 2006, IEEE/ACM International Conference on Computer-Aided Design.

Transformations for functional verification of synthesized designs

Ranga Vemuri, William L. Bradley, 1995, Proceedings of the 8th International Conference on VLSI Design.

A regularity-based hierarchical symbolic analysis method for large-scale analog networks

Alex Doboli, Ranga Vemuri, 2001, DATE '01.

A methodology for rapid prototyping of analog systems

Ranga Vemuri, Sree Ganesan, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

An Integrated Multicomponent Synthesis for MCMs.

Ranga Vemuri, Ning Ren, Praveen Sinha, 1993 .

Hierarchical constraint transformation based on genetic optimization for analog system synthesis

Alex Doboli, Ranga Vemuri, Adrián Núñez-Aldana, 2006, Integr..

Fast Inversions in Small Finite Fields by Using Binary Trees

Ranga Vemuri, Shaohua Tang, Haibo Yi, 2016, Comput. J..

Robust Logic Obfuscation for Trusted Design Synthesis

Ranga Vemuri, Sanjana Sekar, 2019 .

On physical-aware synthesis of vertically integrated 3D systems

Ranga Vemuri, Madhubanti Mukherjee, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

On-line synthesis for partially reconfigurable FPGAs

Ranga Vemuri, Renqiu Huang, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Using WAVES for Boundary-Scan Architectures

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework

Ranga Vemuri, Angan Das, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Performance verification using partial evaluation and interval analysis

Ranga Vemuri, Jeffrey Walrath, W. Bradley, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Automatic constraint transformation with integrated parameter space exploration in analog system synthesis

Ranga Vemuri, Adrián Núñez-Aldana, Nagu R. Dhanwada, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis

Ranga Vemuri, Huiying Yang, R. Vemuri, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Cone Based Clustering for List Scheduling Algorithms

Ranga Vemuri, Sriram Govindarajan, R. Vemuri, 1997 .

A retiming based relaxation heuristic for resource-constrained loop pipelining

Ranga Vemuri, Vinoo Srinivasan, 1998, Proceedings Eleventh International Conference on VLSI Design.

Configurable workload generators for multicore architectures

Ranga Vemuri, Annie Avakian, Amayika Panda, 2011, 2011 IEEE International SOC Conference.

Selective light V th hopping (SLITH): bridging the gap between runtime dynamic and leakage power reduction

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2009 .

Hierarchical memory synthesis in reconfigurable computers

Ranga Vemuri, Iyad Ouaiss, 2002 .

Hardware software partitioning with integrated hardware design space exploration

Ranga Vemuri, Vinoo Srinivasan, Shankar Radhakrishnan, 1998, Proceedings Design, Automation and Test in Europe.

Mitigating information leakage during critical communication using S*FSM

Ranga Vemuri, Mike Borowczak, R. Vemuri, 2019, IET Comput. Digit. Tech..

Data flow graph partitioning to reduce communication cost

Ranga Vemuri, Christos A. Papachristou, Cris Koutsougeras, 1986, MICRO 19.

Performance Specification and Measurement

Ranga Vemuri, Ram Mandayam, 1993, CHDL.

Adaptive Sampling and Modeling of Analog Circuit Performance Parameters

Ranga Vemuri, Glenn Wolfe, Mengmeng Ding, 2003, VLSI-SOC.

Genetic synthesis: performance-driven logic synthesis using genetic evolution

Ranga Vemuri, Ram Vemuri, R. Vemuri, 1991, [1991] Proceedings. First Great Lakes Symposium on VLSI.

Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design

Ranga Vemuri, Vijay Sundaresan, Srividhya Rammohan, 2008, 21st International Conference on VLSI Design (VLSID 2008).

MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators

Ranga Vemuri, Hemanth Sampath, R. Vemuri, 2003, VLSI-SOC.

A two-level modeling approach to analog circuit performance macromodeling

Ranga Vemuri, Mengmeng Ding, 2005, Design, Automation and Test in Europe.

A hierarchical register optimization algorithm for behavioral synthesis

Ranga Vemuri, Srinivas Katkoori, Jay Roy, 1996, Proceedings of 9th International Conference on VLSI Design.

Sensitivity analysis of a cluster-based interconnect model for FPGAs

Ranga Vemuri, Renqiu Huang, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

Symbolic evaluation of performance models for tradeoff visualization

Ranga Vemuri, Jeffrey Walrath, 1997, DAC.

High- Level Synlthesis System

Ranga Vemuri, N. Kumar, Iayanta Roy, 1992 .

Assertion Coverage Aware Trace Signal Selection in Post-Silicon Validation

Ranga Vemuri, Xiaobang Liu, 2019, 20th International Symposium on Quality Electronic Design (ISQED).

Complete WAVES/VHDL Integration

Ranga Vemuri, James P. Hanna, Robert G. Hillman, 1997 .

Analog-digital partitioning for field-programmable mixed signal systems

Ranga Vemuri, Sree Ganesan, 2001, Proceedings 2001 Conference on Advanced Research in VLSI. ARVLSI 2001.

Accurate estimation of vector dependent leakage power in the presence of process variations

Ranga Vemuri, Romana Fernandes, 2009, 2009 IEEE International Conference on Computer Design.

GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis

Ranga Vemuri, Angan Das, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Secure controllers: Requirements of S*FSM

Ranga Vemuri, Mike Borowczak, 2013, 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS).

Algorithms for coupling circuit and physical synthesis with high-level design-space exploration for 2d and 3d systems

Ranga Vemuri, M. Mukherjee, 2004 .

The GAPLA: a globally asynchronous locally synchronous FPGA architecture

Ranga Vemuri, Xin Jia, 2005, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05).

Area Fragmentation in Reconfigurable Operating Systems

Ranga Vemuri, Manish Handa, R. Vemuri, 2004, ERSA.

A Heterogeneous Cache Distribution with Reconfigurable Interconnect

Ranga Vemuri, Annie Avakian, Aishwariya Pattabiraman, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

On the verification of synthesized designs using automatically generated transformational witnesses

Ranga Vemuri, Rajesh Radhakrishnan, Elena Teica, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration

Ranga Vemuri, Richa Agrawal, Mike Borowczak, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

An iterative algorithm for battery-aware task scheduling on portable computing platforms

Ranga Vemuri, Jawad Khan, 2005, Design, Automation and Test in Europe.

Finite state machine verification on MIMD machines

Ranga Vemuri, Nand Kumar, R. Vemuri, 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

Deep State Encryption for Sequential Logic Circuits

Ranga Vemuri, Yasaswy Kasarabada, Sudheer Ram Thulasi Raman, 2019, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Resource constrained RTL partitioning for synthesis of multi-FPGA designs

Ranga Vemuri, Nand Kumar, Madhavi Vootukuru, 1997, Proceedings Tenth International Conference on VLSI Design.

Towards a specification notation for high-level synthesis of mixed-signal and analog systems

Alex Doboli, Ranga Vemuri, 2000, Proceedings 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation.

On the Use of Hash Tables for Efficient Analog Circuit Synthesis

Ranga Vemuri, Almitra Pradhan, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Automatic precondition verification for high-level design transformations

Ranga Vemuri, A. Sridhar, 1990, IEEE International Symposium on Circuits and Systems.

A methodology for application-specific NoC architecture generation in a dynamic task structure environment

Ranga Vemuri, Balasubramanian Sethuraman, 2009, GLSVLSI '09.

SLED: Sequential Logic Encryption Using Dynamic Keys

Ranga Vemuri, Yasaswy Kasarabada, Vaishali Muralidharan, 2020, 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS).

On state encoding against power analysis attacks for finite state controllers

Ranga Vemuri, Richa Agrawal, 2018, 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Aggressive Runtime Leakage Control Through Adaptive Light-Weight $V_{\rm th}$ Hopping With Temperature and Process Variation

Ranga Vemuri, Wen-Ben Jone, Hao Xu, 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design Constraint Based Attacks

Ranga Vemuri, Suyuan Chen, 2021 .

Defenses Against Design Constraint Based Attacks

Ranga Vemuri, Suyuan Chen, 2021 .

Defenses Against Satisfiability Based Attacks

Ranga Vemuri, Suyuan Chen, 2021 .

Split Manufacturing of Integrated Circuits for Hardware Security and Trust

Ranga Vemuri, Suyuan Chen, 2021 .

SoC Trust Validation Using Assertion-Based Security Monitors

Ranga Vemuri, Khitam Alatoun, Bharath Shankaranarayanan, 2021, 2021 22nd International Symposium on Quality Electronic Design (ISQED).

Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati

Ranga Vemuri, Carla Purdy, Rashmi Jha, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

Security Analysis of a System-on-Chip Using Assertion-Based Verification

Ranga Vemuri, Padmaja Bhamidipati, Shanmukha Murali Achyutha, 2021, 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS).

Split Manufacturing Methods

Ranga Vemuri, Suyuan Chen, R. Vemuri, 2021 .

Logic Encryption for Resource Constrained Designs

Ranga Vemuri, David M. Luria, 2021, IEEE Access.

Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip

Ranga Vemuri, Xiaobang Liu, Padmaja Bhamidipati, 2021, 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Satisfiability Based Attacks

Ranga Vemuri, Suyuan Chen, R. Vemuri, 2021 .

Efficient Methods for SoC Trust Validation Using Information Flow Verification

Ranga Vemuri, Khitam M. Alatoun, Shanmukha Murali Achyutha, 2021, 2021 IEEE 39th International Conference on Computer Design (ICCD).

RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns

Ranga Vemuri, Karam S. Chatha, R. Vemuri, 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

A Performance Modeling and Analysis Environment for Reconngurable Computers

Ranga Vemuri, R. Vemuri, 1998 .