H. Peter Hofstee

发表

High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor

David F. Heidel, Sang H. Dhong, H. Peter Hofstee, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Distributed Sorting

H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut, 1990, Sci. Comput. Program..

Power-constrained microprocessor design

H. Peter Hofstee, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Understanding Systems and Architectures for Big Data

Yan Li, H. Peter Hofstee, Jian Li, 2012 .

Analyzing In-Memory Hash Join: Granularity Matters

H. Peter Hofstee, Jan Hidders, Jinho Lee, 2017, ADMS@VLDB.

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Sang H. Dhong, H. Peter Hofstee, Joel Silberman, 2007, IBM J. Res. Dev..

Cell Broadband Engine Processor

H. Peter Hofstee, 2011, Encyclopedia of Parallel Computing.

Cell Broadband Engine processor vault security architecture

H. Peter Hofstee, Kanna Shimizu, John S. Liberty, 2007, IBM J. Res. Dev..

A 690 ps read-access latency register file for a GHz integer microprocessor

Sang H. Dhong, H. Peter Hofstee, Joel Silberman, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Introduction to the Cell multiprocessor

H. Peter Hofstee, T. R. Maeurer, James A. Kahle, 2005, IBM J. Res. Dev..

A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys

Ting Wang, H. Peter Hofstee, Gordon C. Fossum, 2018, ISC Workshops.

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow

H. Peter Hofstee, Zaid Al-Ars, Jeroen van Straten, 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

H. Peter Hofstee, Sanjay Gupta, Juergen Pille, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Feature detection for image analytics via FPGA acceleration

H. Peter Hofstee, Gi-Joon Nam, Iris Hui-Ru Jiang, 2015, IBM J. Res. Dev..

Second-Generation Big Data Systems

Kevin J. Nowka, H. Peter Hofstee, Fadi H. Gebara, 2015, Computer.

Real-time supercomputing and technology for games and entertainment

H. Peter Hofstee, 2006, SC.

Rome Reborn

H. Peter Hofstee, Gabriele Guidi, Pascal Müller, 2008, SIGGRAPH '08.

Synergistic Processing in Cell's Multicore Architecture

Martin Hopkins, Takeshi Yamazaki, H. Peter Hofstee, 2006, IEEE Micro.

Designing for a gigahertz [guTS integer processor]

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 1998, IEEE Micro.

Heterogeneous Multi-core Processors: The Cell Broadband Engine

H. Peter Hofstee, 2009, Multicore Processors and Systems.

Distributing a Class of Sequential Programs

H. Peter Hofstee, 1992, MPC.

A hardware compilation framework for text analytics queries

Frederick Reiss, H. Peter Hofstee, Heiner Giefers, 2018, J. Parallel Distributed Comput..

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?

H. Peter Hofstee, Chris R. Jesshope, Uzi Vishkin, 2009, Euro-Par Workshops.

Derivation of a rotator circuit with homogeneous interconnect

H. Peter Hofstee, Jun Sawada, 2001, Inf. Process. Lett..

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

H. Peter Hofstee, Atsushi Kameyama, James D. Warnock, 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

The future of multi-core technologies

H. Peter Hofstee, Stephen W. Keckler, Ian Buck, 2007, CLUSTER.

In-memory database acceleration on FPGAs: a survey

H. Peter Hofstee, Jinho Lee, Jian Fang, 2019, The VLDB Journal.

Custom circuit design as a driver of microprocessor performance

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 2000, IBM J. Res. Dev..

USING A CIRCUIT-CENTRIC APPROACH, A SMALL TEAM CONSTRUCTED A GIGAHERTZ INTEGER PROCESSOR , MORE THAN DOUBLING THE FREQUENCY OF FULL -FLEDGED DESIGNS IN THE SAME TECHNOLOGY.

H. Peter Hofstee, Jeffrey L. Burns, Sang Hoo Dhong, 1998 .

A Distributed Implementation of a Task Pool

H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut, 1991, Research Directions in High-Level Parallel Programming Languages.

Distributing a Class of Sequential Programs

H. Peter Hofstee, 1994, Sci. Comput. Program..

PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor

H. Peter Hofstee, Per Stenström, Qijun Wang, 2016, IEEE Computer Architecture Letters.

Power efficient processor architecture and the cell processor

H. Peter Hofstee, H. P. Hofstee, 2005, 11th International Symposium on High-Performance Computer Architecture.

Hardware-accelerated text analytics

Frederick Reiss, H. Peter Hofstee, Christoph Hagleitner, 2014, IEEE Hot Chips Symposium.

Design methodology for a 1.0 GHz microprocessor

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Understanding system design for Big Data workloads

H. Peter Hofstee, Jian Li, Yan Li, 2013, IBM J. Res. Dev..

"Timing closure by design," a high frequency microprocessor design methodology

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 2000, Proceedings 37th Design Automation Conference.

Timed circuit verification using TEL structures

H. Peter Hofstee, Chris J. Myers, Wendy Belluomini, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Communication and Synchronization in the Cell Processor - Invited Talk

H. Peter Hofstee, 2005, CPA.

RAW 2016 Keynotes

H. Peter Hofstee, Patrick Lysaght, Dirk van den Heuvel, 2016, IPDPS Workshops.

The Next 25 Years of Computer Architecture?

H. Peter Hofstee, 2009, Euro-Par Workshops.

Big Data text-oriented benchmark creation for Hadoop

H. Peter Hofstee, Fadi H. Gebara, Anne E. Gattiker, 2013, IBM J. Res. Dev..

Auto-tuning Spark big data workloads on POWER8: Prediction-based dynamic SMT threading

H. Peter Hofstee, Zhen Jia, Jianfeng Zhan, 2016, 2016 International Conference on Parallel Architecture and Compilation Techniques (PACT).

Cell Broadband Engine Processor Design Methodology

Sang H. Dhong, H. Peter Hofstee, Osamu Takahashi, 2007, 2007 IEEE Custom Integrated Circuits Conference.

Preface

H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko, 2007, IBM J. Res. Dev..

Verification of delayed-reset domino circuits using ATACS

H. Peter Hofstee, Chris J. Myers, Wendy Belluomini, 1999, Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

Hardware and software architectures for the CELL processor

H. Peter Hofstee, Michael N. Day, 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator

Kiyoung Choi, H. Peter Hofstee, Heesu Kim, 2017, Proc. VLDB Endow..

Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash

H. Peter Hofstee, Madhusudhan Govindaraju, Rei Odaira, 2016, 2016 IEEE 9th International Conference on Cloud Computing (CLOUD).

CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra

H. Peter Hofstee, Madhusudhan Govindaraju, Rei Odaira, 2018, 2018 IEEE 11th International Conference on Cloud Computing (CLOUD).

Constructing some Distributed Programs

H. Peter Hofstee, 1992 .

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

H. Peter Hofstee, Zaid Al-Ars, Jeroen van Straten, 2021, Journal of Signal Processing Systems.

AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression pdf

H. Peter Hofstee, Zaid Al-Ars, Baozhou Zhu, 2021, IJCAI.

An Attention Module for Convolutional Neural Networks

H. Peter Hofstee, Zaid Al-Ars, Baozhou Zhu, 2021, ICANN.

Adopting OpenCAPI for High Bandwidth Database Accelerators

H. Peter Hofstee, Jan Hidders, Jian Fang, 2017 .