Joel Silberman

发表

High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor

David F. Heidel, Sang H. Dhong, H. Peter Hofstee, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

The circuit design of the synergistic processor element of a CELL processor

Sang H. Dhong, Joel Silberman, Osamu Takahashi, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Thermal analysis of multi-layer functional 3D logic stacks

Joel Silberman, Shurong Tian, Phillip Restle, 2016, 2016 IEEE International 3D Systems Integration Conference (3DIC).

A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias

Joel Silberman, Matthew R. Wordeman, Gary W. Maier, 2012, 2012 IEEE International Solid-State Circuits Conference.

Power-conscious design of the Cell processor's synergistic processor element

Sang H. Dhong, Joel Silberman, Osamu Takahashi, 2005, IEEE Micro.

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI

Sang H. Dhong, H. Peter Hofstee, Joel Silberman, 2007, IBM J. Res. Dev..

A shorted global clock design for multi-GHz 3D stacked chips

Joel Silberman, Liang-Teck Pang, Phillip Restle, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A 690 ps read-access latency register file for a GHz integer microprocessor

Sang H. Dhong, H. Peter Hofstee, Joel Silberman, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Designing for a gigahertz [guTS integer processor]

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 1998, IEEE Micro.

Across the Stack Opportunities for Deep Learning Acceleration

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2018, ISLPED.

Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor

Joel Silberman, Sanjay B. Patel, James Dieffenderfer, 2005, Sixth international symposium on quality electronic design (isqed'05).

Design methodology for a 1.0 GHz microprocessor

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

Sang H. Dhong, Joel Silberman, Osamu Takahashi, 2005, IEEE Micro.

"Timing closure by design," a high frequency microprocessor design methodology

Kevin J. Nowka, Sang H. Dhong, H. Peter Hofstee, 2000, Proceedings 37th Design Automation Conference.

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2018, 2018 IEEE Symposium on VLSI Circuits.

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference

Joel Silberman, Swagath Venkataramani, Matthew M. Ziegler, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

Joel Silberman, Swagath Venkataramani, Vijayalakshmi Srinivasan, 2022, IEEE Journal of Solid-State Circuits.

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling

Joel Silberman, Swagath Venkataramani, Mingu Kang, 2021, 2021 IEEE International Solid- State Circuits Conference (ISSCC).