M. Yoshida

A 17ns 4Mb BICMOS DRAM

Masahiro Yoshida, Masayuki Nakamura, Toshio Maeda, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

WPM 3.7: A 1711s 4Mb CMOS DRAM Using Direct Bit-Line Sensing Technique

Takahiko Hara, Y. Saito, Munehiro Yoshida, 1991 .