R. Chau

发表

Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications

J. Kavalieros, B. Doyle, R. Chau, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications

R. Chau, S. Datta, A. Majumdar, 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..

The ultimate CMOS device and beyond

M. D. Giles, I. Young, K. J. Kuhn, 2012, 2012 International Electron Devices Meeting.

Benchmarking nanotechnology for high-performance and low-power logic transistor applications

R. Chau, M. Metz, M. Radosavljevic, 2004, IEEE Transactions on Nanotechnology.

Emerging silicon and nonsilicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications

J. Kavalieros, B. Doyle, R. Chau, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

A high performance 0.35 /spl mu/m logic technology for 3.3 V and 2.5 V operation

Richard Green, Scott E. Thompson, M. Bohr, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Silicon nanotechnologies and emerging non-silicon nanoelectronics

R. Chau, 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

Carrier Transport in High-Mobility III–V Quantum-Well Transistors and Performance Impact for High-Speed Low-Power Logic Applications

R. Chau, G. Dewey, M. Radosavljevic, 2008, IEEE Electron Device Letters.

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

S. Datta, J. Kavalieros, R. Chau, 2003, IEEE International Electron Devices Meeting 2003.

Ultrahigh-Speed 0 . 5 V Supply Voltage In 0 . 7 Ga 0 . 3 As Quantum-Well Transistors on Silicon Substrate

Suman Datta, J. M. Fastenau, R. Chau, 2009 .

Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (VCC) ranging from 0.5v to 1.0v

R. Chau, G. Dewey, M. Radosavljevic, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Silicon and III-V nanoelectronics

S. Datta, R. Chau, 2005, International Conference on Indium Phosphide and Related Materials, 2005.

Ultrahigh-Speed 0.5 V Supply Voltage $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ Quantum-Well Transistors on Silicon Substrate

S. Datta, R. Chau, G. Dewey, 2007, IEEE Electron Device Letters.

A logic nanotechnology featuring strained-silicon

M. Bohr, S. Sivakumar, Y. El-Mansy, 2004, IEEE Electron Device Letters.

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

S. Datta, S. Hareland, J. Kavalieros, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

A 50 nm depleted-substrate CMOS transistor (DST)

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Novel InSb-based quantum well transistors for ultra-high speed, low power logic applications

S. Datta, T. Ashley, A.R. Barnes, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications

Suman Datta, Martin Trevor Emeny, T. J. Phillips, 2007 .

High-frequency response of 100 nm integrated CMOS transistors with high-K gate dielectrics

J. Kavalieros, B. Doyle, R. Chau, 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al0.83In0.17N/AlN/GaN MOS-HEMT on SiC substrate

J. Kavalieros, R. Chau, G. Dewey, 2013, 2013 IEEE International Electron Devices Meeting.

Heterogeneous integration of enhancement mode in0.7ga0.3as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

S. Datta, J. Kavalieros, R. Chau, 2007, 2007 IEEE International Electron Devices Meeting.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

J. Jopling, M. Agostinelli, C. Prasad, 2008, 2008 IEEE International Reliability Physics Symposium.

Challenges and opportunities of emerging nanotechnology for VLSI nanoelectronics

R. Chau, 2007, 2007 International Semiconductor Device Research Symposium.

Correlation of plasma process induced charging with Fowler-Nordheim stress in p- and n-channel transistors

R. Chau, P. Moon, R. Chau, 1992, 1992 International Technical Digest on Electron Devices Meeting.