B. Jin

Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications

J. Kavalieros, B. Doyle, R. Chau, 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

S. Hareland, J. Kavalieros, B. Doyle, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Emerging silicon and nonsilicon nanoelectronic devices: opportunities and challenges for future high-performance and low-power computational applications

J. Kavalieros, B. Doyle, R. Chau, 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

S. Datta, J. Kavalieros, R. Chau, 2003, IEEE International Electron Devices Meeting 2003.

Silicon nano-transistors and breaking the 10 nm physical gate length barrier

S. Datta, S. Hareland, J. Kavalieros, 2003, 61st Device Research Conference. Conference Digest (Cat. No.03TH8663).

Silicon nano-transistors for logic applications

Suman Datta, Scott Hareland, Brian S. Doyle, 2003 .