H. Bu

Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

I. Hossain, D. Scott, J. Rosal, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Advanced CMOS transistors with a novel HfSiON gate dielectric

H. Bu, R. Khamankar, T. Grider, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

35% drive current improvement from recessed-SiGe drain extensions on 37 nm gate length PMOS

D. T. Grider, H. Bu, Y. Kim, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process

F. Mehrad, H. Bu, L. Colombo, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Modeling the effect of source/drain sidewall spacer process on boron ultra shallow junctions

B. Hornung, H. Bu, A. Jain, 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..