Ning Zhu

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Zhi-Hui Kong, Kiat Seng Yeo, Wang Ling Goh, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Enhanced low-power high-speed probabilistic adders for error-toerant application

Ning. Zhu, Ning Zhu, 2011 .

Enhanced low-power high-speed adder for error-tolerant application

Gang Wang, Kiat Seng Yeo, Ning Zhu, 2009, 2010 International SoC Design Conference.

Ultra low-power high-speed flexible Probabilistic Adder for Error-Tolerant Applications

Kiat Seng Yeo, Ning Zhu, Wang Ling Goh, 2011, 2011 International SoC Design Conference.