Alexandru Plesco

发表

Automatic Generation of FPGA-Specific Pipelined Accelerators

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2011, ARC.

Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool

Alain Darte, Christophe Alias, Alexandru Plesco, 2010, ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors.

High-Level Synthesis of Pipelined FSM from Loop Nests

Fabrice Rastello, Christophe Alias, Alexandru Plesco, 2016 .

FPGA-specific synthesis of loop-nests with pipelined computational cores

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2012, Microprocess. Microsystems.

Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis

Alain Darte, Christophe Alias, Alexandru Plesco, 2011 .

Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA

Alain Darte, Christophe Alias, Alexandru Plesco, 2012, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Data-aware Process Networks

Christophe Alias, Alexandru Plesco, 2015 .

Optimizing remote accesses for offloaded kernels: application to high-level synthesis for FPGA

Alain Darte, Christophe Alias, Alexandru Plesco, 2013, DATE 2013.

Kernel Offloading with Optimized Remote Accesses

Alain Darte, Christophe Alias, Alexandru Plesco, 2011 .

Method for automatic synthesis circuits, device and associated computer program

Christophe Alias, Alexandru Plesco, 2014 .

Optimizing Affine Control With Semantic Factorizations

Christophe Alias, Alexandru Plesco, Christophe Alias, 2017, ACM Trans. Archit. Code Optim..

Automatic Generation of FPGA-Specific Pipelined Accelerators LIP Research Report RR2010-37

Bogdan Pasca, Christophe Alias, Alexandru Plesco, 2010 .

Scientific Foundations - Program analysis and transformations for high-level synthesis

Paul Feautrier, Laure Gonnord, Alain Darte, 2010 .

An FPGA architecture for solving the Table Maker's Dilemma

Jean-Michel Muller, Florent de Dinechin, Bogdan Pasca, 2011, ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors.

New Results - Data-aware Process Networks

Christophe Alias, Alexandru Plesco, 2015 .

Coupling Loop Transformations and High-Level Synthesis

Tanguy Risset, Alexandru Plesco, 2008 .

Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators. (Transformations de programmes et optimisations de l'architecture mémoire pour la synthèse de haut niveau d'accélérateurs matériels)

Alexandru Plesco, 2010 .