Y. Kamatani

A stacked DCFL structure applied to a prescalar IC and investigated for ASICs

Shoichi Shimizu, H. Nagasawa, Y. Kamatani, 1992, GaAs IC Symposium Technical Digest 1992.

A circuit simulator based on the waveform-relaxation method using selective overlapped partition and classified latencies

Y. Kamatani, T. Shima, 1988, 1988., IEEE International Symposium on Circuits and Systems.