S. Dey

发表

Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node

T. P. Dash, S. Dey, S. Das, 2020 .

Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes

C. K. Maiti, S. Dey, S. Das, 2019, 2019 Devices for Integrated Circuit (DevIC).

SPICE Parameter Extraction of Tri-Gate FinFETs-An Integrated Approach

C. K. Maiti, T. P. Dash, S. Dey, 2019, 2019 Devices for Integrated Circuit (DevIC).

Molecular-beam epitaxy growth of device-compatible GaAs on silicon substrates with thin (∼80 nm) Si1-x Gex step-graded buffer layers for high- κ III-V metal-oxide-semiconductor field effect transistor applications

Davood Shahrjerdi, Xiaojun Yu, James S. Harris, 2007 .

A novel 50 nm vertical MOSFET with a dielectric pocket

S. Dey, Sanjay K. Banerjee, S. Banerjee, 2006 .

Improved hot-electron reliability in strained-Si nMOS

C.R. Cleavelin, D. Onsongo, S. Dey, 2004, IEEE Transactions on Electron Devices.

Effects of Hot Carrier Stress on Reliability of Strained-Si Mosfets

M. Agostinelli, C. Prasad, S. Dey, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Pure germanium epitaxial growth on thin strained silicon-germanium graded layers on bulk silicon substrate for high-mobility channel metal-oxide-semiconductor field-effect transistors

S. Dey, S. Banerjee, M. José-Yacamán, 2006 .

Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier

S. Dey, J. Sarkar, S. Dey, 2006, IEEE Transactions on Electron Devices.

Ultra-Thin Si1−xGex Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

Alan Campion, S. Dey, Sanjay K. Banerjee, 2007 .