C. K. Maiti

发表

Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node

T. P. Dash, S. Dey, S. Das, 2020 .

CrossRef Listing of Deleted DOIs

S. C. Pandey, Anindya Maiti, C. K. Maiti, 2009 .

Teaching Technology Computer Aided Design (TCAD) Online

Ananda Maiti, C. K. Maiti, 2012 .

Stress Profile Analysis in n-FinFET Devices

C. K. Maiti, Tara Prasanna Dash, S. Das, 2019, Advances in Intelligent Systems and Computing.

NBTI Degradation and Recovery in Nanowire FETs

C. K. Maiti, Tara Prasanna Dash, S. Das, 2019, 2019 Devices for Integrated Circuit (DevIC).

Random Telegraph Noise characterization of p-type silicon nanowire FinFETs

C. K. Maiti, C. Mukherjee, T. Maiti, 2010, 2010 27th International Conference on Microelectronics Proceedings.

An Explicit Surface-Potential Based Biaxial Strained-Si n-MOSFET Model for Circuit Simulation

C. K. Maiti, A. Banerjee, T. Maiti, 2010 .

Current conduction mechanism in TiO2 gate dielectrics

Milan Bera, C. K. Maiti, S. Chakraborty, 2005 .

Role of Stress/Strain Mapping in Advanced CMOS Process Technology Nodes

C. K. Maiti, Tara Prasanna Dash, S. Das, 2019, 2019 Devices for Integrated Circuit (DevIC).

Stress Analysis in Uniaxially Strained-SiGe Channel FinFETs at 7N Technology Node

C. K. Maiti, Tara Prasanna Dash, S. Das, 2018, 2018 IEEE Electron Devices Kolkata Conference (EDKCON).

Electrical characterization of Ni/sub y/(Si/sub 1-x/Ge/sub x/)/sub 1-y//Si/sub 1-x/Ge/sub x/ and NiSi/Si Schottky diodes

C. K. Maiti, S. Chattopadhyay, S. K. Nandi, 2004, 2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716).

Variability Due to Orientation Dependent Oxide Thickness in SOI-FinFETs

C. K. Maiti, Tara Prasanna Dash, S. Das, 2018, 2018 IEEE Electron Devices Kolkata Conference (EDKCON).

Stress-Engineered AlGaN/GaN High Electron Mobility Transistors Design

C. K. Maiti, Tara Prasanna Dash, S. Das, 2021, 2021 Devices for Integrated Circuit (DevIC).

Effects of substrate strain and electrical stress on lattice dynamics, defects, and traps in strained-Si/Si0.81Ge0.19 n-type metal-oxide-semiconductor field effect transistors

C. K. Maiti, T. Maiti, C. Mukherjee, 2012 .

Effect of silicidation on the electrical characteristics of polycrystalline-SiGe Schottky diode

C. K. Maiti, S. Chattopadhyay, C. Bose, 2006 .

Technology CAD of silicided Schottky barrier MOSFET for elevated source–drain engineering

C. K. Maiti, S. Chattopadhyay, C. Bose, 2005 .

Effect of annealing on interface state density of Ni-silicided/Si1−xGex Schottky diode

C. K. Maiti, G. Dalapati, S. Chattopadhyay, 2005 .

Performance improvement of flash memory using AlN as charge-trapping Layer

S. S. Mahato, C. K. Maiti, C. Mahata, 2009 .

Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2020, Physica Scripta.

Determination of the interface properties of Ni-silicided strained-Si/SiGe heterostructure Schottky diodes using capacitance-voltage technique

C. K. Maiti, S. Chattopadhyay, R. Das, 2006 .

Quantum-mechanical modeling of current-voltage characteristics of Ti-silicided Schottky diodes

C. K. Maiti, A. O'Neill, S. Chattopadhyay, 2006 .

Studies on the Electrical Characteristics of Ni and NiPt-alloy Silicided Schottky Diodes

C. K. Maiti, W. K. Choi, D. Antoniadis, 2005 .

Ge-channel p-MOSFETs with ZrO2 gate dielectrics

C. K. Maiti, S. Chakraborty, S. Mandal, 2005 .

Nanosized Metal-Grain-Granularity Induced Characteristics Fluctuation in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

C. K. Maiti, Tara Prasanna Dash, S. Dey, 2019, International Journal of Nanoscience.

Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes

C. K. Maiti, Tara Prasanna Dash, E. Mohapatra, 2021, SN Applied Sciences.

Performance Analysis of Si-Channel Nanosheet FETs with Strained SiGe Source/Drain Stressors

C. K. Maiti, Tara Prasanna Dash, E. Mohapatra, 2020 .

Simulation of single-event upset in power MOSFETs

C. K. Maiti, C. K. Maiti, Tara Prasanna Dash, 2017, 2017 Devices for Integrated Circuit (DevIC).

Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node

C. K. Maiti, Tara Prasanna Dash, S. Dey, 2019, 2019 Devices for Integrated Circuit (DevIC).

Assessment of heterojunction SiGe tunnel-FET for low-power digital circuits

C. K. Maiti, Tara Prasanna Dash, S. Das, 2017, 2017 Devices for Integrated Circuit (DevIC).

Experimental and simulation study of charge transport mechanism in HfTiOx high-k gate dielectric on SiGe heterolayers

C. K. Maiti, Tara Prasanna Dash, Atanu Bag, 2022, Bulletin of Materials Science.

Effects of hot-carrier degradation on the low frequency noise in strained-Si p-MOSFETs

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2018 .

Silicon Nanowire FinFETs

C. K. Maiti, C. Mukherjee, 2012 .

Stress-induced Degradation and Defect Studies in Strained-Si/SiGe MOSFETs

C. K. Maiti, C. Mukherjee, 2014 .

Silicon Nanowire

C. K. Maiti, C. Mukherjee, 2012 .

Characterization of traps in SiGe:C channel heterojunction PMOSFETs

C. K. Maiti, C. K. Maiti, C. Mukherjee, 2012, Other Conferences.

Performance and Opportunities of Gate-All-Around Vertically-Stacked Nanowire Transistors at 3nm Technology Nodes

C. K. Maiti, Tara Prasanna Dash, S. Dey, 2019, 2019 Devices for Integrated Circuit (DevIC).

Design and simulation of vertically-stacked nanowire transistors at 3 nm technology nodes

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2019, Physica Scripta.

Vertically-Stacked Silicon Nanosheet Field Effect Transistors at 3nm Technology Nodes

C. K. Maiti, S. Dey, S. Das, 2019, 2019 Devices for Integrated Circuit (DevIC).

Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7 nm Technology Nodes

C. K. Maiti, Tara Prasanna Dash, S. Dey, 2019, Journal of Electronic Materials.

SPICE Parameter Extraction of Tri-Gate FinFETs-An Integrated Approach

C. K. Maiti, T. P. Dash, S. Dey, 2019, 2019 Devices for Integrated Circuit (DevIC).

Strain-engineering in nanowire field-effect transistors at 3 nm technology node

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2020 .

Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes

C. K. Maiti, Tara Prasanna Dash, E. Mohapatra, 2023, Physica Scripta.

Performance comparison of strained-SiGe and bulk-Si channel FinFETs at 7 nm technology node

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2019, Journal of Micromechanics and Microengineering.

Channel thermal noise modeling and high frequency noise parameters of tri-gate FinFETs

C. K. Maiti, C. K. Maiti, C. Mukherjee, 2013, Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

Performance enhancement of FinFETs at low temperature

C. K. Maiti, Tara Prasanna Dash, S. Dey, 2017, 2017 Devices for Integrated Circuit (DevIC).

Beyond silicon: Strained-SiGe channel FinFETs

C. K. Maiti, Tara Prasanna Dash, Sanghamitra Das, 2015, 2015 International Conference on Man and Machine Interfacing (MAMI).

Applications of Silicon-Germanium Heterostructure Devices

C. K. Maiti, G. A. Armstrong, C. K. Maiti, 2001 .

Performance Analysis of Sub-10nm Vertically Stacked Gate-All-Around FETs

C. K. Maiti, Tara Prasanna Dash, E. Mohapatra, 2020, 2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS).