S. J. Hillenius

A 6.75ns single level metal CMOS 16x16 multiplier IC

J. M. Andrews, J. A. Michejda, R. Shamz, 1988, Symposium 1988 on VLSI Circuits.

Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology

Mark R. Pinto, P. W. Diodato, S. J. Hillenius, 1998 .

A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology

A. D. Lopez, J. A. Michejda, S. J. Hillenius, 1989 .

A high-performance directly insertable self-aligned ultra-rad-hard and enhanced isolation field-oxide technology for gigahertz silicon NMOS/CMOS VLSI

Kwok K. Ng, R. L. Field, S. J. Hillenius, 1989 .

Anomalous Short-channel Body Coefficients Due To Transient Enhanced Diffusion

M. R. Pinto, C. S. Rafferty, S. J. Hillenius, 1993, [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD).

50 nm Vertical Replacement-Gate (VRG) pMOSFETs

T. Nigam, James D. Plummer, J. F. Miner, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A 2-ghz CMOS Dual-modulus Prescalar Ic

D. M. Boulin, J. M. Andrews, J. A. Michejda, 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

S. J. Hillenius, C. Lu, N. Tsai, 1991 .

Explanation of reverse short channel effect by defect gradients

M. R. Pinto, C. S. Rafferty, S. J. Hillenius, 1993, Proceedings of IEEE International Electron Devices Meeting.

Ultra-high speed CMOS circuits in thin SIMOX films

R. L. Field, George K. Celler, S. J. Hillenius, 1989, International Technical Digest on Electron Devices Meeting.

Rapid thermal anneal induced effects in polycrystalline silicon gate structures

Avid Kamgar, S. J. Hillenius, S. Hillenius, 1987 .