R. Jérisian

发表

Dielectric testing reliability in power integrated circuits

Slimane Oussalah, R. Jérisian, 1998 .

Two‐dimensional modelling and characterization of gate‐to‐drain overlap contribution on the leakage current of a MOSFET, used as a GCD

R. Jérisian, E. Ciantar, S. Burgniard, 1993 .

3-D analysis of the breakdown localised defects of ACS TM through a triac study

Thierry Lequeu, R. Jérisian, Stéphane Forster, 2000 .

A comparative study of different contact resistance test structures dedicated to the power process technology

Boualem Djezzar, Slimane Oussalah, R. Jérisian, 2005 .

Contributions à la connaissance de la fiabilité des composants semiconducteurs de puissance

Thierry Lequeu, Zoubir Khatir, Gerard Coquery, 2005 .

Hot-carrier effects on leakage currents in MOSFETs—Modelling and experiment

R. Jérisian, E. Ciantar, S. Burgniard, 1993 .

On the optimum thickness to test dielectric reliability, in an integrated technology of power devices

Slimane Oussalah, R. Jérisian, F. Nebel, 2000 .