José M. Martínez-Villena

Design environment for hardware generation of SLFF neural network topologies with ELM training capability

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2015, 2015 IEEE 13th International Conference on Industrial Informatics (INDIN).

Hardware implementation of real-time Extreme Learning Machine in FPGA: Analysis of precision, resource occupation and performance

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2016, Comput. Electr. Eng..

Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks

Marek Wegrzyn, José V. Francés, Manuel Bataller-Mompeán, 2016, IEEE Transactions on Industrial Informatics.

Hardware implementation methods in Random Vector Functional-Link Networks

Emilio Soria-Olivas, Alfredo Rosado Muñoz, José M. Martínez-Villena, 2013, Applied Intelligence.

Growing Hierarchical Sectors on Sectors

José David Martín-Guerrero, Emilio Soria-Olivas, Pablo Escandell-Montero, 2011, ESANN.

Analysis of a Reinforcement Learning algorithm using Self-Organizing Maps

José David Martín-Guerrero, Emilio Soria-Olivas, Pablo Escandell-Montero, 2011, ESANN.

Hardware implementation methods in Random Vector Functional-Link Networks

José M. Martínez-Villena, E. Soria-Olivas, A. R. Muñoz, 2014, Applied Intelligence.