Miura Sadahiko

发表

1Mb 4T-2MTJ Nonvolatile STT-RAM for Embedded Memories Using 32b Fine-Grained Power Gating Technique -- Achieves 1.0ns/200ps Wake-Up/Power-Off Times

Hanyu Takahiro, Endoh Tetsuo, Ohno Hideo, 2013 .

A 90-nm Three-terminal MRAM Embedded Nonvolatile Microcontroller for Standby-Power-Critical Applications

Hanyu Takahiro, Sugibayashi Tadahiko, Endoh Tetsuo, 2014 .

a 4Mb MRAM and its experimental application

Sugibayashi Tadahiko, Honda Takeshi, Miura Sadahiko, 2006 .

Highly Reliable Logic Primitive Gates for Spintronics-Based Logic LSI

Hanyu Takahiro, Sugibayashi Tadahiko, Endoh Tetsuo, 2013 .

A 1Mb STT-MRAM for Nonvolatile Embedded Memories performing 1.5ns/2.1ns Random Read/Write Cycle Time -- Background Write (BGW) Scheme applied to a 6T2MTJ Memory Cell

Hanyu Takahiro, Endoh Tetsuo, Ohno Hideo, 2014 .

MRAM technology trend and evolution, 32Mb MRAM development

Kobayashi Yosuke, Ito Yuichi, Sugibayashi Tadahiko, 2009 .

Fabrication of a Nonvolatile TCAM Chip Based on 4T-2MTJ Cell Structure

Hanyu Takahiro, Endoh Tetsuo, Ohno Hideo, 2013 .

1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator

Tanigawa Takaho, Endoh Tetsuo, Ohno Hideo, 2016 .

Low Current Perpendicular Domain Wall Motion Cell for Scalable High-Speed MRAM

Sugibayashi Tadahiko, Miura Sadahiko, Honjo Hiroaki, 2009 .

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

Hanyu Takahiro, Sugibayashi Tadahiko, Endoh Tetsuo, 2014 .