Liangjian Lyu

A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply

Liangjian Lyu, Dawei Ye, C.-J. Richard Shi, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros

Chixiao Chen, Hao Jiang, Qi Liu, 2023, 2023 IEEE International Symposium on Circuits and Systems (ISCAS).

A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission

Liangjian Lyu, Dawei Ye, Rongjin Xu, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.