Heng Quan

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost

Zhiyi Yu, Yan Ying, Liyang Zhou, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms

Zhiyi Yu, Yan Ying, Ming-e Jing, 2012, 2012 IEEE International Solid-State Circuits Conference.

A novel network on chip architecture - Stargon

Zhiyi Yu, Xiaoyang Zeng, Xingxing Zhang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

A novel multi-core processor for communication applications

Zhiyi Yu, Xiaoyang Zeng, Bei Huang, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

The PLL Amplifier Design Based on Analog Multiplier

Jin Chen, Lei Fan, Hui Wang, 2014 .

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array

Yi Li, Jie Lin, Jiajie Zhang, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

Routing Protocol for Heterogeneous Wireless Sensor Networks Based on a Modified Grey Wolf Optimizer

Qiang Gao, Heng Quan, Xiaoqiang Zhao, 2020, Sensors.

A novel vector/SIMD multiply-accumulate unit based on reconfigurable booth array

Zhiyi Yu, Xiaoyang Zeng, Kaidi You, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs

Zhiyi Yu, Xiaoyang Zeng, Zewen Shi, 2011, 2011 9th IEEE International Conference on ASIC.

A 16-Core Processor With Shared-Memory and Message-Passing Communications

Xu Cheng, Jiajie Zhang, Zhiyi Yu, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.