Masao Yanagisawa

发表

Pedestrian navigation based on landmark recognition using glass-type wearable devices

Nozomu Togawa, Masao Yanagisawa, Ryoya Yano, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Implementation evaluation of scan-based attack against a Trivium cipher circuit

Masao Yanagisawa, Nozomu Togawa, Daisuke Oku, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

Nozomu Togawa, Masao Yanagisawa, Kotaro Terada, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs

Masao Yanagisawa, Nozomu Togawa, Koichi Fujiwara, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-Based Side-Channel Attack on the RSA Cryptosystem

Nozomu Togawa, Masao Yanagisawa, Ryuta Nara, 2012 .

Scan-based attack against elliptic curve cryptosystems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

A Locality-Aware Hybrid NoC Configuration Algorithm Utilizing the Communication Volume among IP Cores

Nozomu Togawa, Masao Yanagisawa, Seungju Lee, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters

Hideo Ito, Youhua Shi, Masao Yanagisawa, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, IEICE Trans. Inf. Syst..

A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Depth-Constrained Technology Mapping Algorithm for Logic-Blocks Composed of Tree-Structured LUTs (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1999 .

A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures

Nozomu Togawa, Masao Yanagisawa, Kotaro Terada, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-based Attack against DES and Triple DES Cryptosystems Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Hirokazu Kodera, 2013, J. Inf. Process..

MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012, IEICE Electron. Express.

Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures

Masao Yanagisawa, Nozomu Togawa, Kento Hasegawa, 2020, IEICE Trans. Inf. Syst..

Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms

Nozomu Togawa, Masao Yanagisawa, Koki Igawa, 2016, IEICE Electron. Express.

A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element

Saki Tajima, Youhua Shi, Nozomu Togawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Scan-Based Side-Channel Attack on the LED Block Cipher Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Mika Fujishiro, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A thread partitioning algorithm in low power high-level synthesis

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Partial Redundant Fault Secure High Level Synthesis for RDR Architecture

Nozomu Togawa, Masao Yanagisawa, Sho Tanaka, 2012 .

Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

C-5 A Software/Hardware Codesign for MPEG Encoder

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

Efficient Ising Model Mapping to Solving Slot Placement Problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2019, 2019 IEEE International Conference on Consumer Electronics (ICCE).

Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices

Nozomu Togawa, Masao Yanagisawa, Takashi Takenaka, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

An FPGA Implementation Method based on Distributed-register Architectures

Nozomu Togawa, Masao Yanagisawa, Koichi Fujiwara, 2019, IPSJ Trans. Syst. LSI Des. Methodol..

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests

Masao Yanagisawa, Kazuaki Ishikawa, Nozomu Togawa, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning

Nozomu Togawa, Masao Yanagisawa, Masaru Oya, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hardware/Software Cosynthesis Method for CAM Processor with Area Constraints

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, IPSJ Trans. Syst. LSI Des. Methodol..

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2020, IPSJ Trans. Syst. LSI Des. Methodol..

An incremental placement and global routing algorithm for field-programmable gate arrays

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

Area/delay estimation for digital signal processor cores

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2001, ASP-DAC '01.

VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2013, 2013 IEEE 10th International Conference on ASIC.

Suspicious timing error prediction with in-cycle clock gating

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, International Symposium on Quality Electronic Design (ISQED).

Robust AES circuit design for delay variation using suspicious timing error prediction

Nozomu Togawa, Masao Yanagisawa, Yuki Yahagi, 2017, 2017 International SoC Design Conference (ISOCC).

Personalized one-day travel with multi-nearby-landmark recommendation

Nozomu Togawa, Masao Yanagisawa, Siya Bao, 2017, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Clock skew estimate modeling for FPGA high-level synthesis and its application

Nozomu Togawa, Masao Yanagisawa, Koichi Fujiwara, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Imaging detailed cerebral glucose metabolism in PET using maximum a posterior criterion and pattern recognition : Search algorithm in feature space

Masao Yanagisawa, Akihiko Uchiyama, Jun Yamaguchi, 2006 .

Alternative run-length coding through scan chain reconfiguration for joint minimization of test data volume and power consumption in scan test

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2004, 13th Asian Test Symposium.

Scan-based side-channel attack on Camellia cipher using scan signatures

Nozomu Togawa, Masao Yanagisawa, Hirokazu Kodera, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A High-Level Synthesis Algorithm with Post-Silicon Delay Tuning for RDR Architectures and its Experimental Evaluations

Masao Yanagisawa, Nozomu Togawa, Yuta Hagio, 2013 .

A Fault-Secure High-Level Synthesis Algorithm for RDR Architectures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Throughput driven check point selection in suspicious timing error prediction based designs

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2014, 2014 IEEE 5th Latin American Symposium on Circuits and Systems.

Gesture recognition of air-tapping and its application to character input in VR space

Masao Yanagisawa, Masayuki Yokoyama, Mamoru Hirota, 2018, SIGGRAPH ASIA Posters.

A thread partitioning algorithm in low power high-level synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

GECOM: Test data compression combined with all unknown response masking

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2008, 2008 Asia and South Pacific Design Automation Conference.

A Hardware/Software Cosynthesis Algorithm for Processors with Heterogeneous Datapaths

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

Redesign for untrusted gate-level netlists

Nozomu Togawa, Masao Yanagisawa, Masaru Oya, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests

Nozomu Togawa, Masao Yanagisawa, Kazuaki Ishikawa, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Hardware Trojans classification for gate-level netlists based on machine learning

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Scan-Based Attack against Trivium Stream Cipher Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Mika Fujishiro, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal

Masao Yanagisawa, Tomoyuki Nitta, Nozomu Togawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A landmark-based route recommendation method for pedestrian walking strategies

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

A Scan-Based Attack Based on Discriminators for AES Cryptosystems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams

Nozomu Togawa, Masao Yanagisawa, Ryota Ishikawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2020, 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS).

A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files

Masao Yanagisawa, Nozomu Togawa, Takashi Sakurai, 2001 .

In-situ Trojan authentication for invalidating hardware-Trojan functions

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

A stayed location estimation method for sparse GPS positioning information

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

Dynamically changeable secure scan architecture against scan-based side channel attack

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012, 2012 International SoC Design Conference (ISOCC).

Personalized Landmark Recommendation for Language-Specific Users by Open Data Mining

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2018 .

Bit-write-reducing and error-correcting code generation by clustering error-correcting codewords for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Accurate automated clustering of two-dimensional data for single-nucleotide polymorphism genotyping by a combination of clustering methods: evaluation by large-scale real data

Masao Yanagisawa, Yusuke Nakamura, Toshimasa Yamazaki, 2007, Bioinform..

A robust scan-based side-channel attack method against HMAC-SHA-256 circuits

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2017, 2017 IEEE 7th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

A Reduction Method of Writing Operations to Non-volatile Memory by Keeping Data Difference for Low-Power Circuit Design

Masao Yanagisawa, Shinji Kimura, Hiroyuki Shinohara, 2014 .

A High - level Synthesis Algorithm with Floorplaning for a Distributed - register Architecture

Masao Yanagisawa, Akira Tanaka, Tatsuo Ohtsuki, 2004 .

2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, April 22-24, 2013

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, VLSI-DAT.

A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability

Saki Tajima, Youhua Shi, Masao Yanagisawa, 2019, 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

An FPGA Layout Reconfiguration Algorithm Based on Global Routes for Engineering Changes in System Design Specifications(Special Section on Discrete Mathematics and Its Applications)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

Concurrent faulty clock detection for crypto circuits against clock glitch based DFA

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

Nozomu Togawa, Masao Yanagisawa, Koki Igawa, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits

Nozomu Togawa, Masao Yanagisawa, Ryota Ishikawa, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Simulation-Based Bus Width Optimization for Two-Level Caches

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

Rotator-based multiplexer network synthesis for field-data extractors

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

Indoor navigation based on real-time direction information generation using wearable glasses

Masao Yanagisawa, Tomoyuki Nitta, Kazuaki Ishikawa, 2016, 2016 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia).

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

of a Fast Intra Prediction Algorithm for H.264/ A VC Encoding

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2010 .

A hardware-Trojan classification method utilizing boundary net structures

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Small-sized and noise-reducing power analyzer design for low-power IoT devices

Nozomu Togawa, Masao Yanagisawa, Takashi Takenaka, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Low Power Memory Based Design Method of Constant Multipliers for Digital Filters

Masao Yanagisawa, Shinji Kimura, Tadahiko Sugibayashi, 2013 .

A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

Floorplan-aware High-Level Synthesis for Distributed/Shared-Register Architectures

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

A Fast Selector-Based Subtract-Multiplication Unit and Its Application to Butterfly Unit

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

Greedy Algorithm for the On-Chip Decoupling Capacitance Optimization to Satisfy the Voltage Drop Constraint

Nozomu Togawa, Masao Yanagisawa, Satoshi Goto, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A selector-based FFT processor and its FPGA implementation

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2017, 2017 International SoC Design Conference (ISOCC).

Linear and bi-linear interpolation circuits using selector logics and their evaluations

Nozomu Togawa, Masao Yanagisawa, Masashi Shio, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Instruction set and functional unit synthesis for SIMD processor cores

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions

Nozomu Togawa, Masao Yanagisawa, Toshinori Takayama, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems

Nozomu Togawa, Masao Yanagisawa, Daiki Asai, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Floorplan-Driven High-Level Synthesis for Distributed/Shared-Register Architectures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2008, IPSJ Trans. Syst. LSI Des. Methodol..

A proposal for wearable controller device and finger gesture recognition using surface electromyography

Masao Yanagisawa, Masayuki Yokoyama, Mamoru Hirota, 2017, SIGGRAPH ASIA.

VLSI architecture for a flexible motion estimation with parameters

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Fast Motion Estimation Scheme for Video Coding Using Feature Vector Matching and Motion Vector's Correlations

Masao Yanagisawa, Tatsuo Ohtsuki, Tingrong Zhao, 1999, J. Circuits Syst. Comput..

Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Energy-efficient High-level Synthesis for HDR Architectures

Nozomu Togawa, Masao Yanagisawa, Shin-ya Abe, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2019, 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Scan-based attack on the LED block cipher using scan signatures

Nozomu Togawa, Masao Yanagisawa, Mika Fujishiro, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Write Reduction of Internal Registers for Non-volatile RISC Processors

Masao Yanagisawa, Shinji Kimura, Tomoya Goto, 2014 .

Fast source optimization by clustering algorithm based on lithography properties

Nozomu Togawa, Masao Yanagisawa, Toshiya Kotani, 2015, Advanced Lithography.

Integrating Wearable Sensor Technology into Project-management Process

Masao Yanagisawa, Kazuo Yano, Nobuo Sato, 2012, J. Inf. Process..

An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A bit-write reduction method based on error-correcting codes for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2015, The 20th Asia and South Pacific Design Automation Conference.

Improved scan-based side-channel attack on the LED block cipher independent of scan structure

Nozomu Togawa, Masao Yanagisawa, Mika Fujishiro, 2014 .

A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

High-level area/delay/power estimation for low power system VLSIs with gated clocks

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A high-level synthesis system for digital signal processing based on enumerating data-flow graphs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1998, Proceedings of 1998 Asia and South Pacific Design Automation Conference.

A low cost and high speed CSD-based symmetric transpose block FIR implementation

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Fast Module Placement in Floorplan-aware High-level Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

An Adder-Segmentation-based FIR for High Speed Signal Processing

Youhua Shi, Masao Yanagisawa, Jinghao Ye, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A Hardware Engine for Generation Deformed Map

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

An Area/Delay Estimation Technique for Control - Based Hardware Synthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2001 .

A hardware/software partitioning algorithm for processor cores of digital signal processing

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

Personalized Landmark Recommendation Algorithm Based on Language-specific Satisfaction Prediction Using Heterogeneous Open Data Sources

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2018, 2018 10th International Conference on Computational Intelligence and Communication Networks (CICN).

Scan Vulnerability in Elliptic Curve Cryptosystems (IPSJ Transactions on System LSI Design Methodology Vol.4)

Masao Yanagisawa, Nozomu Togawa, Ryuta Nara, 2011 .

Two-level Cache Simulation with L2 Unified Cache for Embedded Applications

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

A Fast Elliptic Curve Cryptosystem LSI Embedding Word-Based Montgomery Multiplier

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2006, IEICE Trans. Electron..

Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Road-illuminance level inference across road networks based on Bayesian analysis

Nozomu Togawa, Masao Yanagisawa, Siya Bao, 2018, 2018 IEEE International Conference on Consumer Electronics (ICCE).

Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Robust estimation of the arterial input function for Logan plots using an intersectional searching algorithm and clustering in positron emission tomography for neuroreceptor imaging

Masao Yanagisawa, Yuichi Kimura, Keiichi Oda, 2008, NeuroImage.

Soft error tolerant latch designs with low power consumption (invited paper)

Saki Tajima, Youhua Shi, Nozomu Togawa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks

Youhua Shi, Masao Yanagisawa, Lin Ye, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An area/time optimizing algorithm in high-level synthesis for control-based hardwares (short paper)

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2000, ASP-DAC '00.

Area and delay estimation in hardware/software cosynthesis for digital signal processor cores

Nozomu Togawa, Masao Yanagisawa, Yuichiro Miyaoka, 2001 .

A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n)

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2008, 2008 Asia and South Pacific Design Automation Conference.

A visible corner-landmark based route finding algorithm for pedestrian navigation

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

Effective write-reduction method for MLC non-volatile memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Unknown response masking with minimized observable response loss and mask data

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2008, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems.

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design

Nozomu Togawa, Masao Yanagisawa, Koki Igawa, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices

Masao Yanagisawa, Masayuki Yokoyama, Ryohei Koyama, 2017, J. Sensors.

A Simultaneous Placement and Global Routing Algorithm for FPGAs with Power Optimization

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999, J. Circuits Syst. Comput..

A Fast Weighted Adder by Reducing Partial Product for Reconstruction in Super-Resolution

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

Localization of sperm whales in a group using clicks received at two separated short baseline arrays.

Masao Yanagisawa, Harumi Sugimatsu, Tamaki Ura, 2010, The Journal of the Acoustical Society of America.

A selective scan chain reconfiguration through run-length coding for test data compression and scan power reduction

Youhua Shi, Masao Yanagisawa, Tatsuo Ohtsuki, 2004 .

Speeding-up exact and fast FIFO-based cache configuration simulation

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2011, IEICE Electron. Express.

Consideration of A Bluetooth Network Scheme in Public Area based on Reducing a Hand-off Time

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information

Nozomu Togawa, Masao Yanagisawa, Kazuaki Ishikawa, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Scan-Based Side-Channel Attack against RSA Cryptosystems Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices

Nozomu Togawa, Masao Yanagisawa, Takashi Takenaka, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments

Masao Yanagisawa, Nozomu Togawa, Siya Bao, 2019, ICIS.

An L1 Cache Design Space Exploration System for Embedded Applications

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A loop structure optimization targeting high-level synthesis of fast number theoretic transform

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Bicycle Behavior Recognition using Sensors Equipped with Smartphone

Nozomu Togawa, Masao Yanagisawa, Kazuaki Ishikawa, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach

Nozomu Togawa, Masao Yanagisawa, Yuki Kobayashi, 2018, 2018 IEEE 8th International Conference on Consumer Electronics - Berlin (ICCE-Berlin).

An area/time optimizing algorithm in high-level synthesis for control-based hardwares

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

An Ising model mapping to solve rectangle packing problem

Nozomu Togawa, Masao Yanagisawa, Daisuke Oku, 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Weighted-Sum Circuit Using Selector Logic By Transforming Bit-Level Operations

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2009 .

A write-reducing and error-correcting code generation method for non-volatile memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A delay variation and floorplan aware high-level synthesis algorithm with body biasing

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

FPGA-Based Reconfigurable Adaptive FEC

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

Secure scan design using improved random order and its evaluations

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A Delay-variation-aware High-level Synthesis Algorithm for RDR Architectures

Nozomu Togawa, Masao Yanagisawa, Yuta Hagio, 2014, IPSJ Trans. Syst. LSI Des. Methodol..

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Floorplan-driven High-Level Synthesis Algorithm for Reducing Multiplexer Inputs Targeting FPGAs

Masao Yanagisawa, Nozomu Togawa, Koichi Fujiwara, 2014 .

High-level power optimization based on thread partitioning

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2004 .

A Retargetable Simulator Generator for DSP Processor Cores with Packed SIMD-type Instructions

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

Masao Yanagisawa, Nozomu Togawa, Shinji Kimura, 2013 .

A Behavioral Synthesis System for Extended CAM Processors

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

Weighted adders with selector logics for super-resolution and its FPGA-based evaluation

Nozomu Togawa, Masao Yanagisawa, Hiromine Yoshihara, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Hardware Trojans classification for gate-level netlists using multi-layer neural networks

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

An interface-circuit synthesis method with configurable processor core in IP-based SoC designs

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2006, Asia and South Pacific Conference on Design Automation, 2006..

A Secure Test Technique for Pipelined Advanced Encryption Standard

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2008, IEICE Trans. Inf. Syst..

Suspicious timing error prediction using check points

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013 .

1P1-A12 Autonomous inspection of support legs of on-water platforms by AUVs : Relative localization based on sonar and camera

Masao Yanagisawa, Toshihiro Maki, Tamaki Ura, 2009 .

A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation

Youhua Shi, Masao Yanagisawa, Tatsuo Ohtsuki, 2003 .

A simultaneous placement and global routing algorithm for FPGAs with power optimization

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998, IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242).

Scan-based attack against DES cryptosystems using scan signatures

Nozomu Togawa, Masao Yanagisawa, Hirokazu Kodera, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A hardware/software cosynthesis system for digital signal processor cores with two types of register files

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 1999 .

A processor core synthesis system in IP-based SoC design

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2005, ASP-DAC.

An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2002, Asia-Pacific Conference on Circuits and Systems.

A Hardware/Software Partitioning Framework for SIMD Processor Cores

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2007 .

A High-Level Synthesis System for Digital Signal Processing Based on Data-Flow Graph Enumeration (Special Section on VLSI Design and CAD Algorithms)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

FCSCAN: an efficient multiscan-based test compression technique for test cost reduction

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2006, Asia and South Pacific Conference on Design Automation, 2006..

Partitioning-based multiplexer network synthesis for field-data extractors

Nozomu Togawa, Masao Yanagisawa, Yutaka Tamiya, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs

Nozomu Togawa, Masao Yanagisawa, Koichi Fujiwara, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n)

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement

Nozomu Togawa, Masao Yanagisawa, Ryota Ishikawa, 2018, 2018 New Generation of CAS (NGCAS).

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation

Nozomu Togawa, Masao Yanagisawa, Keita Igarashi, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

State-dependent changeable scan architecture against scan-based side channel attacks

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

An energy-efficient high-level synthesis algorithm for huddle-based distributed-register architectures

Nozomu Togawa, Masao Yanagisawa, Shin-ya Abe, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An Algorithm and a Flexible Architecture for Fast Block-Matching Motion Estimation

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing

Youhua Shi, Masao Yanagisawa, Jinghao Ye, 2019, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Design-for-secure-test for crypto cores

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2009, 2009 International Test Conference.

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Nozomu Togawa, Masao Yanagisawa, Koichi Fujiwara, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating

Nozomu Togawa, Masao Yanagisawa, Shin-ya Abe, 2014, IPSJ Trans. Syst. LSI Des. Methodol..

Energy-efficient high-level synthesis for HDR architectures with clock gating

Nozomu Togawa, Masao Yanagisawa, Hiroyuki Akasaka, 2012, 2012 International SoC Design Conference (ISOCC).

A Control/Data Flow Graph Transformation Algorithm in High-Level Synthesis for Control-Based Hardwares

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

A Hardware/Software Cosynthesis System for Processors with Content Addressable Memory

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 1998 .

A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

Masao Yanagisawa, Nozomu Togawa, Kotaro Terada, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis

Nozomu Togawa, Masao Yanagisawa, Siya Bao, 2018, 2018 IEEE International Conference on Big Data (Big Data).

A safe and comprehensive route finding method for pedestrian based on lighting and landmark

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.

Instruction set and functional unit synthesis for SIMD processor cores

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Scan-based attack against Trivium stream cipher independent of scan structure

Nozomu Togawa, Masao Yanagisawa, Mika Fujishiro, 2013, 2013 IEEE 10th International Conference on ASIC.

An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hardware/Software Partitioning Algorhithm for Image Processors with a Packed SIMD Type Instruction Set

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2002 .

Energy-efficient High-level Synthesis Considering Clock Design for HDR Architectures

Nozomu Togawa, Masao Yanagisawa, Hiroyuki Akasaka, 2012 .

A cosynthesis algorithm for application specific processors with heterogeneous datapaths

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Scan Vulnerability in Elliptic Curve Cryptosystems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2011, IPSJ Trans. Syst. LSI Des. Methodol..

A-6-5 Evaluation of A Floorplan-aware High-level Synthesis Algorithm Optimizing Critical Path for FPGA Designs

Masao Yanagisawa, Nozomu Togawa, Kazushi Kawamura, 2016 .

Secure Scan Architecture Using State Dependent Scan Flip-Flop with Key-Based Configuration on RSA Circuit

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012 .

Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures

Nozomu Togawa, Masao Yanagisawa, Hirokazu Kodera, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

System Architecture based on Hardware/Software Codesign for Optimization of Video Encoders

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2003 .

Muscle analysis of hand and forearm during tapping using surface electromyography

Masao Yanagisawa, Masayuki Yokoyama, Ryohei Koyama, 2015, 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE).

A Multiplexer Reduction Algorithm in High-level Synthesis for Distributed-Register Architectures

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2008 .

A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures

Nozomu Togawa, Masao Yanagisawa, Kotaro Terada, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A-6-3 Reduction of Rewriting Routing Switches for Reconfiguration of NanoBridge Based FPGA

Masao Yanagisawa, Shinji Kimura, Kohei Aoki, 2016 .

Exact and fast L1 cache simulation for embedded systems

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2009, 2009 Asia and South Pacific Design Automation Conference.

Hardware Trojan detection and classification based on steady state learning

Nozomu Togawa, Masao Yanagisawa, Masaru Oya, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Bi-Partitioning Based Multiplexer Network for Field-Data Extractors

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Designing hardware trojans and their detection based on a SVM-based approach

Nozomu Togawa, Masao Yanagisawa, Kento Hasegawa, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs

Youhua Shi, Masao Yanagisawa, Nozomu Togawa, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A Temperature-Aware High-Level Synthesis Algorithm for Regular-Distributed-Register Architectures based on Accurate Energy Consumption Estimation

Masao Yanagisawa, Nozomu Togawa, Kazushi Kawamura, 2012 .

Greedy Optimization Algorithm for the Power/Ground Network Design to Satisfy the Voltage Drop Constraint

Nozomu Togawa, Masao Yanagisawa, Satoshi Goto, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons

Nozomu Togawa, Masao Yanagisawa, Tomoyuki Nitta, 2017, 2017 IEEE 6th Global Conference on Consumer Electronics (GCCE).

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

CAM Processor Synthesis Based on Behavioral Descriptions (Special Section on VLSI Design and CAD Algorithms)

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2000 .

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching

Nozomu Togawa, Masao Yanagisawa, Yukiyasu Tsunoo, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Area/Delay Estimation Method for an Application Processor in HW/SW Cosynthesis

Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa, 2006 .

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A partial redundant fault-secure high-level synthesis algorithm for RDR architectures

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

High-level synthesis with post-silicon delay tuning for RDR architectures

Nozomu Togawa, Masao Yanagisawa, Yuta Hagio, 2013, 2013 International SoC Design Conference (ISOCC).

Scan-based side-channel attack against symmetric key ciphers using scan signatures

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

Secure Scan Design with Dynamically Configurable Connection

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, 2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing.

A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems

Masao Yanagisawa, Masayoshi Tachibana, Tatsuo Ohtsuki, 2009 .

Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy

Youhua Shi, Masao Yanagisawa, Jinghao Ye, 2020, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Exposure source optimization by clustering for lithography

Nozomu Togawa, Masao Yanagisawa, Toshiya Kotani, 2014 .

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Fast and Exact Cache Configuration Simulation for Two-core L1 Cache

Nozomu Togawa, Masao Yanagisawa, Masashi Tawada, 2012 .

Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone

Nozomu Togawa, Masao Yanagisawa, Toshinori Takayama, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling

Nozomu Togawa, Masao Yanagisawa, Shin-ya Abe, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

Scan-Based Attack on AES through Round Registers and Its Countermeasure

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A score-based classification method for identifying Hardware-Trojans at gate-level netlists

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation

Nozomu Togawa, Masao Yanagisawa, Kazushi Kawamura, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Error Correction Coding of Stochastic Numbers Using BER Measurement

Masao Yanagisawa, Nozomu Togawa, Masashi Tawada, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A Two-Level Cache Design Space Exploration System for Embedded Applications

Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow

Youhua Shi, Masao Yanagisawa, Jinghao Ye, 2021, IEEE Access.

New correction algorithms for multiple comparisons in case-control multilocus association studies based on haplotypes and diplotype configurations

Masao Yanagisawa, Yusuke Nakamura, Naoyuki Kamatani, 2008, Journal of Human Genetics.

Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages

Youhua Shi, Nozomu Togawa, Masao Yanagisawa, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..