A. Sudo

Extending trench DRAM technology to 0.15 /spl mu/m groundrule and beyond

J. Ning, J. Alsmeier, G. Bronner, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)

Y. Toyoshima, H. Yoshimura, S. Matsuda, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions

S. Sawada, H. Ishiuchi, F. Matsuoka, 1992, 1992 International Technical Digest on Electron Devices Meeting.