Y. Urakawa

Characterization of speed and stability of BiNMOS gates with a bipolar and PMOSFET merged structure

Kenji Maeguchi, T. Maeda, Hisayo Sasaki Momose, 1990, International Technical Digest on Electron Devices.

Data-line wiring delay reduction techniques for high-speed BiCMOS SRAM's

K. Ochii, H. Kato, Y. Urakawa, 1991, 1991 Symposium on VLSI Circuits.

A reverse base current under high level injection and its influence on BiCMOS circuit

M. Matsui, T. Maeda, Hisayo Sasaki Momose, 1991, International Electron Devices Meeting 1991 [Technical Digest].

11.5ns 1M x 1/256K x 4TTL BiCMOS SRAM's with voltage- and temperature-compensated interfaces

A. Suzuki, T. Hamano, K. Sato, 1989, Symposium 1989 on VLSI Circuits.