V. Seshadri

发表

Base-delta-immediate compression: Practical data compression for on-chip caches

Onur Mutlu, Todd C. Mowry, Gennady Pekhimenko, 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

X-RiSAWOZ: High-Quality End-to-End Multilingual Dialogue Datasets and Few-shot Agents

Gaël de Chalendar, Sina J. Semnani, Vivek Seshadri, 2023, ACL.

Language Translation as a Socio-Technical System:Case-Studies of Mixed-Initiative Interactions

Tanuja Ganu, Monojit Choudhury, Vivek Seshadri, 2021, COMPASS.

Exploring Crowdsourced Work in Low-Resource Settings

Colin Scott, Indrani Medhi-Thies, Joyojeet Pal, 2019, CHI.

PipeDream: generalized pipeline parallelism for DNN training

Nikhil R. Devanur, Amar Phanishayee, Gregory R. Ganger, 2019, SOSP.

Multilingual and code-switching ASR challenges for low resource Indian languages pdf

Samarth Bharadwaj, Chiranjeevi Yarra, Prasanta Kumar Ghosh, 2021, Interspeech.

Compiling KB-sized machine learning models to tiny IoT devices

Vivek Seshadri, Rahul Sharma, Sridhar Gopinath, 2019, PLDI.

MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications

Vivek Seshadri, Steve Wilton, Aayan Kumar, 2021, 2021 31st International Conference on Field-Programmable Logic and Applications (FPL).

In-DRAM Bulk Bitwise Execution Engine pdf

Onur Mutlu, Vivek Seshadri, Vivek Seshadri, 2019, ArXiv.

Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology

Onur Mutlu, Todd C. Mowry, Phillip B. Gibbons, 2017, 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms

Rachata Ausavarungnirun, Onur Mutlu, Samira Manabi Khan, 2017, SIGMETRICS.

BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling

Onur Mutlu, Donghyuk Lee, Vivek Seshadri, 2016, IEEE Transactions on Parallel and Distributed Systems.

ChargeCache: Reducing DRAM latency by exploiting row access locality

Onur Mutlu, Oguz Ergin, Gennady Pekhimenko, 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).

The application slowdown model: Quantifying and controlling the impact of inter-application interference at shared caches and main memory

Onur Mutlu, Samira Manabi Khan, Arnab Ghosh, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Gather-Scatter DRAM: In-DRAM address translation to improve the spatial locality of non-unit strided accesses

Onur Mutlu, Todd C. Mowry, Phillip B. Gibbons, 2015, 2015 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

The Blacklisting Memory Scheduler: Achieving high performance and fairness at low cost

Onur Mutlu, Donghyuk Lee, Vivek Seshadri, 2014, 2014 IEEE 32nd International Conference on Computer Design (ICCD).

RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization

Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu, 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Tiered-latency DRAM: A low latency and low cost DRAM architecture

Onur Mutlu, Donghyuk Lee, Yoongu Kim, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

MISE: Providing performance predictability and improving fairness in shared main memory systems

Onur Mutlu, Yoongu Kim, Vivek Seshadri, 2013, 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA).

A case for exploiting subarray-level parallelism (SALP) in DRAM

Onur Mutlu, Donghyuk Lee, Yoongu Kim, 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

RowClone: Fast and Efficient In-DRAM Copy and Initialization of Bulk Data

Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu, 2013 .

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

Gennady Pekhimenko, Vivek Seshadri, O. Mutlu, 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).

Dataplant: Enhancing System Security with Low-Cost In-DRAM Value Generation Primitives

Jeremie S. Kim, Vivek Seshadri, O. Mutlu, 2019, 1902.07344.

Simple DRAM and Virtual Memory Abstractions to Enable Highly Efficient Memory Systems pdf

Vivek Seshadri, Vivek Seshadri, V. Seshadri, 2016, ArXiv.

Fast Bulk Bitwise AND and OR in DRAM

Onur Mutlu, Todd C. Mowry, Phillip B. Gibbons, 2015, IEEE Computer Architecture Letters.

Chapter Four - Simple Operations in Memory to Reduce Data Movement

Onur Mutlu, Vivek Seshadri, Vivek Seshadri, 2017, Adv. Comput..

RowClone: Accelerating Data Movement and Initialization Using DRAM pdf

Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu, 2018, ArXiv.

Buddy-RAM: Improving the Performance and Efficiency of Bulk Bitwise Operations Using DRAM pdf

Onur Mutlu, Todd C. Mowry, Phillip B. Gibbons, 2016, ArXiv.

The Processing Using Memory Paradigm: In-DRAM Bulk Copy, Initialization, Bitwise AND and OR pdf

Onur Mutlu, Vivek Seshadri, Vivek Seshadri, 2016, ArXiv.

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems pdf

Onur Mutlu, Yoongu Kim, Vivek Seshadri, 2018, ArXiv.

Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins pdf

Onur Mutlu, Samira Manabi Khan, Gennady Pekhimenko, 2018, ArXiv.

Adaptive-Latency DRAM (AL-DRAM) pdf

Kevin Kai-Wei Chang, Onur Mutlu, Samira Manabi Khan, 2016, ArXiv.

Aksharantar: Towards building open transliteration tools for the next billion users

Mitesh M. Khapra, Vivek Seshadri, Pratyush Kumar, 2022, ArXiv.

Linearly compressed pages: A low-complexity, low-latency main memory compression framework

Onur Mutlu, Todd C. Mowry, Gennady Pekhimenko, 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

Feeling Proud, Feeling Embarrassed: Experiences of Low-income Women with Crowd Work

Rama Adithya Varanasi, Vivek Seshadri, Aditya Vashistha, 2022, CHI.

Shiftry: RNN inference in 2KB of RAM

Vivek Seshadri, Rahul Sharma, Aayan Kumar, 2020, Proc. ACM Program. Lang..

Exploiting Row-Level Temporal Locality in DRAM to Reduce the Memory Access Latency pdf

Onur Mutlu, Oguz Ergin, Gennady Pekhimenko, 2018, ArXiv.

Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism pdf

Onur Mutlu, Donghyuk Lee, Yoongu Kim, 2018, ArXiv.

Design-Induced Latency Variation in Modern DRAM Chips

Gennady Pekhimenko, Vivek Seshadri, O. Mutlu, 2016, Proc. ACM Meas. Anal. Comput. Syst..

Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips pdf

Rachata Ausavarungnirun, Onur Mutlu, Samira Manabi Khan, 2016, ArXiv.

The Dirty-Block Index

Onur Mutlu, Todd C. Mowry, Phillip B. Gibbons, 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

PipeDream: Fast and Efficient Pipeline Parallel DNN Training pdf

Nikhil R. Devanur, Amar Phanishayee, Gregory R. Ganger, 2018, ArXiv.

The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework

Rachata Ausavarungnirun, Onur Mutlu, Saugata Ghose, 2020, 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA).

NVOverlay: Enabling Efficient and Scalable High-Frequency Snapshotting to NVM

Todd C. Mowry, Gennady Pekhimenko, Michael A. Kozuch, 2021, 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA).