Jincheng Yang

A 1-V 5.2–5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS

Liyuan Liu, Nanjian Wu, Zhao Zhang, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter

Jian Liu, Liyuan Liu, Nanjian Wu, 2017, IEICE Electron. Express.

A 8×8 compact SRAM in 65nm standard CMOS technology

Nanjian Wu, Peng Feng, Jincheng Yang, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A 18-to-23 GHz −253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique

Jian Liu, Liyuan Liu, Nanjian Wu, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 0.9–2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique

Liyuan Liu, Nanjian Wu, Peng Feng, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Optimal dispatching method for power system load response based on operational risk

Kai Zhang, Zhijun Long, Changhong Deng, 2017, 2017 IEEE Conference on Energy Internet and Energy System Integration (EI2).