Jinde Vijay Kumar

Design and development of FPGA based low power pipelined 64-Bit RISC processor with double precision floating point unit

Jinde Vijay Kumar, Boya Nagaraju, Chinthakunta Swapna, 2014, 2014 International Conference on Communication and Signal Processing.

FPGA Based Implementation of Pipelined 32-bit RISC Processor with Floating Point Unit

Jinde Vijay Kumar, Boya Nagaraju, Chintakunta Swapna, 2014 .