S. Hatano

A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board Simulatig Actual Memory Module

H. Osaka, Y. Uematsu, Y. Nishio, 2007, 2007 IEEE Electrical Performance of Electronic Packaging.

Low-cost, Low-noise Vref Design for High-speed DDR Memory Modules

Y. Uematsu, H. Osaka, S. Hatano, 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

Design and development of optical fiber joining techniques for efficient construction of aerial distribution cable systems

S. Hatano, M. Takaya, Toshiaki Katagiri, 1997 .