R. Shankar

Conditional Clocking Flip-Flop for Low Power High-Speed Mobile Application SOC

N. Jayapal, D. Karthikeyan, A. Lakshminarayanan, 2014 .

Demonstration of Charge Trap Flash Bit-Cell in 180nm CMOS Logic Foundry

U. Ganguly, H.S. Jatana, R. Shankar, 2018, 2018 4th IEEE International Conference on Emerging Electronics (ICEE).

Modelling and Simulation for Damping of Power System Network Oscillations by Meticulous Tuning of PSS Parameters Employed in DAVR of Practical Alternators

Atchayaram Nalini, E. Sheeba Percis, R. Shankar, 2019 .

Timing jitter analysis of a multi-wavelength all-optical regenerator

Ting Wang, Yue-Kai Huang, Lei Xu, 2007, 2007 IEEE Sarnoff Symposium.