A. Ramkaj

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog–Digital Corrections in 28-nm CMOS

Marcel J. M. Pelgrom, Marian Verhelst, Michiel S. J. Steyaert, 2020, IEEE Journal of Solid-State Circuits.

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK–OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS

M. Steyaert, F. Tavernier, A. Ramkaj, 2019, IEEE Solid-State Circuits Letters.

A 56 GS/s 8-bit 0.011 mm2 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS

P. Caragiulo, B. Murmann, A. Arbabian, 2022, ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC).

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Michiel S. J. Steyaert, Filip Tavernier, Maarten Strackx, 2018, IEEE Journal of Solid-State Circuits.