Rohit Kapur

发表

Rohit Kapur, R. Chandramouli, Thomas W. Williams, 2001, IEEE Des. Test Comput..

Speed binning with path delay test in 150-nm technology

Rohit Kapur, Bruce Cory, Bill Underwood, 2003, IEEE Design & Test of Computers.

A new methodology for improved tester utilization

Rohit Kapur, Thomas W. Williams, Ajay Khoche, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Directed-binary search in logic BIST diagnostics

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Aggresive scan chain masking for improved diagnosis of multiple scan chain failures

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2013, 2013 18th IEEE European Test Symposium (ETS).

IP and Automation to Support IEEE P1500

Rohit Kapur, Mike Ricchetti, Dwayne Burek, 2001, VTS.

Bounded Adjacent Fill for Low Capture Power Scan Testing

Rohit Kapur, Anshuman Chandra, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits pdf

Rohit Kapur, Santanu Chattopadhyay, Rajit Karmakar, 2018, ArXiv.

Historical Perspective on Scan Compression

Rohit Kapur, Thomas W. Williams, Subhasish Mitra, 2008, IEEE Design & Test of Computers.

Conference Reports

Rohit Kapur, 2010, IEEE Design & Test of Computers.

Predicting Scan Compression IP Configurations for Better QoR

Rohit Kapur, Jyotirmoy Saikia, Pramod Notiyath, 2011, 2011 Asian Test Symposium.

Bounding Signal Probabilities for Testability Measurement Using Conditional Syndromes

M. Ray Mercer, Rohit Kapur, 1992, IEEE Trans. Computers.

Enhancing test efficiency for delay fault testing using multiple-clocked schemes

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 2002, DAC '02.

Overview of the IEEE P1500 standard

Yervant Zorian, Rohit Kapur, Karim Arabi, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Enhancing security of logic encryption using embedded key generation unit

Rohit Kapur, Santanu Chattopadhyay, Rajit Karmakar, 2017, 2017 International Test Conference in Asia (ITC-Asia).

Security vs. test quality: are they mutually exclusive?

Rohit Kapur, 2004, 2004 International Conferce on Test.

Proactive management of X's in scan chains for compression

Rohit Kapur, Anshuman Chandra, Yasunari Kanzawa, 2009, 2009 10th International Symposium on Quality Electronic Design.

High level ATPG is important and is on its way!

Rohit Kapur, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Iddq testing for high performance CMOS-the next ten years

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 1996, Proceedings ED&TC European Design and Test Conference.

CTL for Test Information of Digital ICS

Rohit Kapur, 2002 .

A weighted random pattern test generation system

Rohit Kapur, Thomas W. Williams, Srinivas Patil, 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On using IEEE P1500 SECT for test plug-n-play

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

Deterministic Shift Power Reduction in Test Compression

Rohit Kapur, Rishi Kumar, Kanad Basu, 2017, VDAT.

A reconfigurable shared scan-in architecture

Rohit Kapur, Thomas W. Williams, Frederic Neuveux, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction

Rohit Kapur, Anshuman Chandra, Felix Ng, 2008, 2008 Design, Automation and Test in Europe.

P1500-CTL: Towards a Standard Core Test Language

Rohit Kapur, M. Lousberg, B. Koenemann, 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

CHEOPS: cost-driven heuristic for partial scan

Rohit Kapur, Magdy Abadir, Joe Newman, 1992 .

A Case Study on Implementing Compressed DFT Architecture

Rohit Kapur, Anshuman Chandra, Subramanian Chebiyam, 2014, 2014 IEEE 23rd Asian Test Symposium.

Iddq test: sensitivity analysis of scaling

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

Designing efficient combinational compression architecture for testing industrial circuits

Rohit Kapur, Anshuman Chandra, Santosh Kulkarni, 2015, 2015 19th International Symposium on VLSI Design and Test.

Changing the scan enable during shift

Rohit Kapur, Thomas W. Williams, Frederic Neuveux, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

Aggressive Exclusion of Scan Flip-Flops from Compression Architecture for Better Coverage and Reduced TDV: A Hybrid Approach

Rohit Kapur, Pralhadrao V. Shantagiri, 2019 .

A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2012, 2012 25th International Conference on VLSI Design.

TRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING

Ann Q. Gates, Doris L. Carver, Rohit Kapur, 2005 .

Design for testability in nanometer technologies; searching for quality

Rohit Kapur, Thomas W. Williams, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

Efficient compression of deterministic patterns into multiple PRPG seeds

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2005, IEEE International Conference on Test, 2005..

Minimizing the Impact of Scan Compression

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Fast seed computation for reseeding shift register in test pattern compression

Rohit Kapur, Nahmsuk Oh, T. W. Williams, 2002, ICCAD 2002.

DFT MAX and Power

Rohit Kapur, Thomas W. Williams, Peter Wohl, 2007, J. Low Power Electron..

Interval Based X-Masking for Scan Compression Architectures

Rohit Kapur, Anshuman Chandra, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Test the test experts: do we know what we are doing?

Rohit Kapur, 2005, IEEE International Conference on Test, 2005..

Tester retargetable patterns

Rohit Kapur, Thomas W. Williams, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Fundamentals of timing information for test: How simple can we get?

Rohit Kapur, Thomas W. Williams, Jindrich Zejda, 2007, 2007 IEEE International Test Conference.

CTL the language for describing core-based test

Rohit Kapur, Brion L. Keller, Maurice Lousberg, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Functional approaches to generating orderings for efficient symbolic representations

Don E. Ross, M. Ray Mercer, Rohit Kapur, 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

The Mutating Metric for Benchmarking Test

Rohit Kapur, Thomas W. Williams, Cy Hay, 2000, IEEE Des. Test Comput..

Not All Xs are Bad for Scan Compression

Rohit Kapur, Anshuman Chandra, 2008, 2008 17th Asian Test Symposium.

Breaking the Test Application Time Barriers in Compression: Adaptive Scan-Cyclical (AS-C)

Rohit Kapur, Anshuman Chandra, Jyotirmoy Saikia, 2011, 2011 Asian Test Symposium.

Conference Reports

Rohit Kapur, 2010, IEEE Des. Test Comput..

DFT closure

Rohit Kapur, Thomas W. Williams, D. Hsu, 2000, Proceedings of the Ninth Asian Test Symposium.

Limitations in predicting defect level based on stuck-at fault coverage

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 1994, Proceedings of IEEE VLSI Test Symposium.

Towards a standard for embedded core test: an example

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

CTL and Its Usage in the EDA Industry

Rohit Kapur, Brion L. Keller, Sandeep Bhatia, 2009, IEEE Design & Test of Computers.

Small Test Set Generation with High Diagnosability

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2016, J. Circuits Syst. Comput..

Conference Reports

Rohit Kapur, 2010, IEEE Des. Test Comput..

Cost-Driven Ranking of Memory Elements for Partial Intrusion

Rohit Kapur, Magdy S. Abadir, 1997, IEEE Des. Test Comput..

Innovative practices session 10C: Advances in DFT and compression

Irith Pomeranz, Rohit Kapur, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Analysis of delay test effectiveness with a multiple-clock scheme

M. Ray Mercer, Rohit Kapur, Thomas W. Williams, 2002, Proceedings. International Test Conference.

OCI: Open Compression Interface

Rohit Kapur, Brion L. Keller, Benoit Nadeau-Dostie, 2006, 2006 IEEE International Test Conference.

All Tests for a Fault are Not Eyually Valuable for Defect Detection

M. Ray Mercer, Rohit Kapur, Jaehong Park, 1992, Proceedings International Test Conference 1992.

Fault diagnosis in designs with extreme low pin test data compressors

Rohit Kapur, Subhadip Kundu, Parthajit Bhattacharya, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

3D-Scalable Adaptive Scan (3D-SAS)

Rohit Kapur, Krishnendu Chakrabarty, Anshuman Chandra, 2012, 2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International.

Special session 5B: Panel How much toggle activity should we be testing with?

Mark Mohammad Tehranipoor, Rohit Kapur, Xiaoqing Wen, 2011, 29th VLSI Test Symposium.

Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set

Rohit Kapur, Rishi Kumar, Subhadip Kundu, 2017, 2017 IEEE International Test Conference (ITC).

Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Testing in the Year 2020

Rohit Kapur, Antonio Rubio, Rajesh Galivanche, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams

Don E. Ross, M. Ray Mercer, Kenneth M. Butler, 1991, 28th ACM/IEEE Design Automation Conference.

Security vs. test quality: are they mutually exclusive?

Rohit Kapur, 2004 .

Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2011, 2011 24th Internatioal Conference on VLSI Design.

System Test and Reliability: Techniques for Avoiding Failure (Guest Editors' Introduction)

Rohit Kapur, Edward F. Miller, R. Kapur, 1996, Computer.

Test pattern compression using prelude vectors in fan-out scan chain with feedback architecture

Rohit Kapur, Thomas W. Williams, Nahmsuk Oh, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Predictive solutions for test - The next DFT paradigm?

Rohit Kapur, Chris Allsup, 2009 .

On IEEE P1500's Standard for Embedded Core Test

Yervant Zorian, Rohit Kapur, Erik Jan Marinissen, 2002, J. Electron. Test..

Design of an efficient weighted random pattern generation system

Rohit Kapur, Thomas W. Williams, Srinivas Patil, 1994, Proceedings., International Test Conference.

A New Logic Encryption Strategy Ensuring Key Interdependency

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2017, 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID).

Designing effective scan compression solutions for industrial circuits

Rohit Kapur, Anshuman Chandra, Subramanian Chebiyam, 2015, Sixteenth International Symposium on Quality Electronic Design.

Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction

Haihua Yan, Rohit Kapur, Anshuman Chandra, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

A Metric for Test Set Characterization and Customization Toward Fault Diagnosis

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scalable Adaptive Scan (SAS)

Rohit Kapur, Anshuman Chandra, Yasunari Kanzawa, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

The roles of controllability and observability in design for test

Don E. Ross, M. Ray Mercer, Kenneth M. Butler, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Manufacturing test of SoCs

Rohit Kapur, Thomas W. Williams, 2002, Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02)..

A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits

Rohit Kapur, Santanu Chattopadhyay, Rajit Karmakar, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Fast seed computation for reseeding shift register in test pattern compression

Rohit Kapur, Thomas W. Williams, Nahmsuk Oh, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Tough Challenges as Design and Test Go Nanometer - Guest Editors' Introduction

Rohit Kapur, Thomas W. Williams, 1999, Computer.

Integrating DFT in the physical synthesis flow

Rohit Kapur, R. Chandramouli, Frederic Neuveux, 2002, Proceedings. International Test Conference.

GA based diagnostic test pattern generation for transition faults

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2015, 2015 19th International Symposium on VLSI Design and Test.

Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors

Rohit Kapur, Subhadip Kundu, Parthajit Bhattacharya, 2016, 2016 IEEE International Test Conference (ITC).

An ATE assisted DFD technique for Volume Diagnosis of scan chains

Rohit Kapur, Santanu Chattopadhyay, Indranil Sengupta, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Handling Unknown with Blend of Scan and Scan Compression

Rohit Kapur, Pralhadrao V. Shantagiri, 2018, J. Electron. Test..

Evaluation of Entropy Driven Compression Bounds on Industrial Designs

Rohit Kapur, Thomas W. Williams, Rubin A. Parekhji, 2008, 2008 17th Asian Test Symposium.

Accurately Determining Bridging Defects from Layout

Qing Su, Rohit Kapur, Thomas W. Williams, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Unifying scan compression

Rohit Kapur, Anshuman Chandra, Pramod Notiyath, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

New scan compression approach to reduce the test data volume

Rohit Kapur, Chandrasekar Shastry, Pralhadrao V. Shantagiri, 2021, IET Comput. Digit. Tech..