S. M. Yasser Sherazi

发表

Low Power Analog and Digital (7,5) Convolutional Decoders in 65 nm CMOS

John B. Anderson, Reza Meraji, S. M. Yasser Sherazi, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS

Andreas Peter Burg, Oskar Andersson, Joachim Neves Rodrigues, 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).

Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS

Oskar Andersson, Joachim Neves Rodrigues, S. M. Yasser Sherazi, 2011, 2011 NORCHIP.

Supply-voltage down conversion for digital CMOS designs

S. M. Yasser Sherazi, Peter Nilsson, Mohammed Azher Ali, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain

Joachim Neves Rodrigues, S. M. Yasser Sherazi, Henrik Sjöland, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Benchmarking of Standard-Cell Based Memories in the Sub-$V_{\rm T}$ Domain in 65-nm CMOS Technology

Andreas Peter Burg, Joachim Neves Rodrigues, S. M. Yasser Sherazi, 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Power savings in digital filters for wireless communication

S. M. Yasser Sherazi, Peter Nilsson, Anusha Gundarapu, 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

A digital baseband for low power FSK based receiver in 65 nm CMOS

S. M. Yasser Sherazi, Henrik Sjöland, Peter Nilsson, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Analog and digital approaches for an energy efficient low complexity channel decoder

John B. Anderson, Reza Meraji, S. M. Yasser Sherazi, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Reduction of Substrate Noise in Sub Clock Frequency Range

Mark Vesterbacka, S. M. Yasser Sherazi, Erik Backenius, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Energy Characterization of RISC processors in the Sub-V T Domain

Joachim Neves Rodrigues, S. M. Yasser Sherazi, Chenxin Zhang, 2011 .

Ultra low power transceivers for wireless sensors and body area networks

John B. Anderson, Ove Edfors, Joachim Neves Rodrigues, 2014, 2014 8th International Symposium on Medical Information and Communication Technology (ISMICT).

Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain

Joachim Neves Rodrigues, S. M. Yasser Sherazi, Henrik Sjöland, 2013, Microprocess. Microsystems.

A Receiver Architecture for Devices in Wireless Body Area Networks

Ove Edfors, Joachim Neves Rodrigues, Reza Meraji, 2012, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Unsupervised machine learning based CD-SEM image segregator for OPC and process window estimation

Sandip Halder, S. M. Yasser Sherazi, Kasem Khalil, 2020 .

Synthesis strategies for sub-VT systems

Andreas Peter Burg, Oskar Andersson, Joachim Neves Rodrigues, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS

Joachim Neves Rodrigues, S. M. Yasser Sherazi, Henrik Sjöland, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).