N. Guitard

ESD design challenges in 28nm hybrid FDSOI/Bulk advanced CMOS process

C. Fenouillet-Beranger, H. Beckrich, P. Galy, 2012, Electrical Overstress / Electrostatic Discharge Symposium Proceedings 2012.

TCAD and SPICE modeling help solve ESD protection issues in analog CMOS technology

P. Perdu, M. Bafleur, N. Guitard, 2003, Microelectron. Reliab..

Different Failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

N. Nolhier, P. Perdu, V. Pouget, 2005, Microelectron. Reliab..

First demonstration of a full 28nm high-k/metal gate circuit transfer from Bulk to UTBB FDSOI technology through hybrid integration

G. Bidal, N. Planes, O. Weber, 2013, 2013 Symposium on VLSI Circuits.

ESD induced latent defects in CMOS ICs and reliability impact

P. Perdu, M. Bafleur, D. Tremouilles, 2004, 2004 Electrical Overstress/Electrostatic Discharge Symposium.