Masatoshi Tsuge

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

Keiichi Higeta, Yuichi Ito, Takashi Kawamoto, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme

Akio Koyama, Masatoshi Tsuge, Makio Uchida, 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

Keiichi Higeta, Yuichi Ito, Takashi Kawamoto, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).