Takeo Yamashita

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

Keiichi Higeta, Yuichi Ito, Takashi Kawamoto, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

WP 25.3 A 450MHz 64b RISC Processor using Multiple Threshold Voltage CMOS

Keiichi Higeta, Takashi Matsumoto, Nobuo Tamba, 2000 .

Neuron-MOS Parallel Search Hardware for Real-Time Signal Processing

Tadashi Shibata, Tadahiro Ohmi, Tsutomu Nakai, 1997 .

Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing

Tadashi Shibata, Tadahiro Ohmi, Tatsuo Morimoto, 1995, NIPS.

Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors

Tadashi Shibata, Koji Kotani, Tadahiro Ohmi, 1993, NIPS.

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

Keiichi Higeta, Yuichi Ito, Takashi Kawamoto, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS

Kazuo Yano, Naoki Kato, Teruhisa Shimizu, 2000 .