Witold A. Pleskacz

发表

Design of a Wideband Low Noise Amplifier for a FMCW Synthetic Aperture Radar in 130 nm SiGe BiCMOS Technology

Daniel Pietron, Igor Butryn, Lukasz Wiechowski, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations

Witold A. Pleskacz, Tomasz Borejko, W. Pleskacz, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

The integrated transmitter and receiver modules for pulse oximeter system

Adam Jarosz, Jerzy Wasowski, Witold A. Pleskacz, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Various MDCT implementations in 0.35μ CMOS

Witold A. Pleskacz, Peter Malík, Marcel Baláz, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Design and Verification Environment for RISC-V Processor Cores

Witold A. Pleskacz, Adrian Oleksiak, Sebastian Cieslak, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

Layout to Logic Defect Analysis for Hierarchical Test Generation

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Elektrogustometr uniwersalny EG-2 ☆

Witold A. Pleskacz, Andrzej Wałkanis, Michał Czesak, 2011 .

SENSAT-a practical tool for estimation of the IC layout sensitivity to spot defects

Witold A. Pleskacz, Wieslaw Kuzmicz, 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model

Witold A. Pleskacz, Krzysztof Marcinek, 2013, Microprocess. Microsystems.

Monitoring of dynamic movements using acceleration measurements

Witold A. Pleskacz, Arkadiusz W. Luczyk, Konrad Neneman, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Estimation of Probability of Different Functional Faults Caused by Spot Defects in VLSI Circuits

Witold A. Pleskacz, Wieslaw Kuzmicz, M. Blyzniuk, 2000 .

Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures

Witold A. Pleskacz, Arkadiusz W. Luczyk, Artur L. Sobczyk, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

MODULE LEVEL DEFECT SIMULATION IN DIGITAL CIRCUITS

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001 .

DefSim: A Remote Laboratory for Studying Physical Defects in CMOS Digital Circuits

Artur Jutman, Witold A. Pleskacz, Tomasz Borejko, 2008, IEEE Transactions on Industrial Electronics.

Dedicated chip for pulse oximetry measurements

Adam Jarosz, Jerzy Wasowski, Witold A. Pleskacz, 2016, 2016 IEEE East-West Design & Test Symposium (EWDTS).

Ka Band Digitally Controlled Oscillator for FMCW Radar in 130 nm SiGe BiCMOS Technology

Daniel Pietron, Igor Butryn, Lukasz Wiechowski, 2018, 2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES).

Importance of on-chip inductor modeling in radio frequency integrated circuits

Daniel Pietron, Witold A. Pleskacz, Tomasz Borejko, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies

Witold A. Pleskacz, Tomasz Borejko, Jacek Gradzki, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A low sampling frequency switched capacitor low-pass filter for wireless receivers

Lukasz Wiechowski, Witold A. Pleskacz, Krzysztof Siwiec, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology

Witold A. Pleskacz, Jakub Kopanski, Dariusz Pienkowski, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications

Witold A. Pleskacz, Tomasz Borejko, Aleh Halauko, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

CAD tool for PLL Design

Witold A. Pleskacz, Tomasz Borejko, Krzysztof Siwiec, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Instruction set extension for software defined radio in mobile GNSS applications

Witold A. Pleskacz, Krzysztof Marcinek, 2013, Electron Technology Conference.

DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology

Witold A. Pleskacz, Tomasz Borejko, Adam Borkowski, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Daniel Pietron, Igor Butryn, Lukasz Wiechowski, 2020, Sensors.

UVM-based Verification of Bluetooth Low Energy Controller

Witold A. Pleskacz, Maciej Moskala, Patryk Kloczko, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Architecture and design of a Bluetooth Low Energy Controller

Witold A. Pleskacz, Patryk Kloczko, Marek Cieplucha, 2016, 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems.

Enhanced LEON3 Low Power IP Core for DSM technologies

Witold A. Pleskacz, Arkadiusz W. Luczyk, Krzysztof Marcinek, 2009, 2009 MIXDES-16th International Conference Mixed Design of Integrated Circuits & Systems.

DEFECT ORIENTED FAULT COVERAGE OF 100% STUCK-AT FAULT TEST SETS

Witold A. Pleskacz, Wieslaw Kuzmicz, M. Blyzniuk, 2000 .

2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique

Witold A. Pleskacz, Krzysztof Siwiec, Szymon Reszewicz, 2018, 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Power Dissipation in Basic Global Clock Distribution Networks

Witold A. Pleskacz, Arkadiusz W. Luczyk, Artur L. Sobczyk, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Estimation Of The Usefulness Of Test Vector Components For Detecting Faults Resulting From Shorts In Standard Cells M.

Witold A. Pleskacz, Wieslaw Kuzmicz, M. Lobur, 2000 .

Foreword to the special issue on 20th IEEE international symposium on design and diagnostics of electronic circuits and systems (DDECS2017)

Ondrej Novák, Witold A. Pleskacz, Zoran Stamenkovic, 2018, Microelectron. Reliab..

A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits

Wojciech Maly, Witold A. Pleskacz, Charles H. Ouyang, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069

Daniel Pietron, Igor Butryn, Lukasz Wiechowski, 2020, Sensors.

Hierarchical test generation for combinational circuits with real defects coverage

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2002, Microelectron. Reliab..

Simulink model of GFSK demodulator based on time-to-digital converter

Lukasz Wiechowski, Witold A. Pleskacz, Krzysztof Siwiec, 2014, 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES).

Multistage low ripple charge pump

Witold A. Pleskacz, Andrzej Grodzicki, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Temperature calibration technique based on on-chip resistor

Witold A. Pleskacz, Krzysztof Siwiec, Pawel Narczyk, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems

Witold A. Pleskacz, Krzysztof Marcinek, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Design of a True Random Number Generator Based on Low Power Oscillator with Increased Jitter

Witold A. Pleskacz, Krzysztof Siwiec, Mariusz Derlecki, 2019, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

EIA/TIA-485 transceiver in standard 130 nm CMOS technology

Witold A. Pleskacz, Krzysztof Siwiec, Michal Wysocki, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

LC-VCO design automation tool for nanometer CMOS technology

Witold A. Pleskacz, Tomasz Borejko, Krzysztof Siwiec, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Analog front-end for precise human body temperature measurement

Witold A. Pleskacz, Krzysztof Siwiec, Pawel Narczyk, 2017, 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS

Witold A. Pleskacz, Tomasz Borejko, Jacek Gradzki, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Enhanced LEON3 core for superscalar processing

Witold A. Pleskacz, Arkadiusz W. Luczyk, Krzysztof Marcinek, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Implementation of the ADELITE Microcontroller for Biomedical Applications

Witold A. Pleskacz, Andrzej Wielgus, Krzysztof Marcinek, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Principal component analysis of accelerations in human dynamic movements: A sample set length effect study

Witold A. Pleskacz, Arkadiusz W. Luczyk, Konrad Neneman, 2017, 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems.

Defect-oriented test- and layout-generation for standard-cell ASIC designs

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2005, 8th Euromicro Conference on Digital System Design (DSD'05).

Defect Analysis and probability evaluation for improving test generation

Witold A. Pleskacz, 2003 .

Integer-N phase locked loop for bluetooth receiver in CMOS 130 nm technology

Igor Butryn, Witold A. Pleskacz, Krzysztof Siwiec, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001, Microelectron. Reliab..

Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication

Witold A. Pleskacz, Krzysztof Marcinek, Lukasz Ostrowski, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio

Witold A. Pleskacz, Peter Malík, Marcel Baláz, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Improvement of integrated circuit testing reliability by using the defect based approach

Witold A. Pleskacz, Dominik Kasprowicz, 2003, Microelectron. Reliab..

Defect-oriented fault simulation and test generation in digital circuits

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Extraction of critical areas for opens in large VLSI circuits

Wojciech Maly, Witold A. Pleskacz, Charles H. Ouyang, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Yield estimation of VLSI circuits with downscaled layouts

Witold A. Pleskacz, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

CAD at the design-manufacturing interface

Wojciech Maly, Witold A. Pleskacz, Pranab K. Nag, 1997, DAC.

New architecture of the object-oriented functional coverage mechanism for digital verification

Witold A. Pleskacz, Marek Cieplucha, 2016, 2016 1st IEEE International Verification and Security Workshop (IVSW).

Characterization of CMOS sequential standard cells for defect based voltage testing

Witold A. Pleskacz, Andrzej Wielgus, 2008, Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08).

DOT: new deterministic defect-oriented ATPG tool

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2005, European Test Symposium (ETS'05).

Controllable Local ClockSignal Generator forDeepSubmicron GALSArchitectures

Witold A. Pleskacz, Arkadiusz W. Luczyk, Artur L. Sobczyk, 2008 .

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology

Witold A. Pleskacz, Tomasz Borejko, Mariusz Derlecki, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

BioSoC: Highly integrated System-on-Chip for health monitoring

Adam Jarosz, Witold A. Pleskacz, Andrzej Wielgus, 2016, 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Retargeting the MIPS-II CPU Core to the RISC-V Architecture

Witold A. Pleskacz, Adrian Oleksiak, Sebastian Cieslak, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications

Witold A. Pleskacz, Tomasz Borejko, Krzysztof Siwiec, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Study of real CMOS defects using DefSim educational environment

Witold A. Pleskacz, 2011, 2011 11th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM).

CMOS standard cells characterization for defect based testing

Witold A. Pleskacz, Wieslaw Kuzmicz, Dominik Kasprowicz, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

CMOS standard cells characterization for I/sub DDQ/ testing

Witold A. Pleskacz, Wieslaw Kuzmicz, Tomasz Borejko, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology

Witold A. Pleskacz, Tomasz Borejko, Viera Stopjaková, 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC

Raimund Ubar, Jaan Raik, Witold A. Pleskacz, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Intermediate frequency filter calibration method for radio frequency receivers in modern CMOS technologies

Witold A. Pleskacz, Krzysztof Siwiec, Aleksander Koter, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Implementation of the Bluetooth receiver RF front-end in the CMOS-RF 130 nm technology

Daniel Pietron, Witold A. Pleskacz, Krzysztof Siwiec, 2014, 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES).

A Low Ripple Current Mode Voltage Doubler

Witold A. Pleskacz, Andrzej Grodzicki, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing

Witold A. Pleskacz, Zbigniew Piatek, Jerzy F. Kolodziejski, 2007, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems.

Configurable MBIST Processor for Embedded Memories Testing

Witold A. Pleskacz, Krzysztof Marcinek, Andrzej A. Wojciechowski, 2019, 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems".

A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring

Adam Jarosz, Witold A. Pleskacz, Andrzej Wielgus, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

Improved yield model for submicron domain

Wojciech Maly, Witold A. Pleskacz, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Detection of yield trends

Wojciech Maly, Witold A. Pleskacz, Hans T. Heineken, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Design and measurements of the specialized VLSI circuit for blood oxygen saturation monitoring

Jerzy Wasowski, Witold A. Pleskacz, Tomasz Borejko, 2017, 2017 14th International Conference The Experience of Designing and Application of CAD Systems in Microelectronics (CADSM).

Class AB Operational Amplifier in CMOS 55 nm Technology

Witold A. Pleskacz, Pawel Pienczuk, Mateusz Teodorowski, 2021, 2021 28th International Conference on Mixed Design of Integrated Circuits and System.