J. Sparso

A Fully Parallel VLSI-implementation of the Viterbi Decoding Algorithm

J. Sparso, H. N. Jorgensen, E. Paaske, 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

O. Paker, J. Sparso, N. Haandbaek, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

Design and performance analysis of delay insensitive multi-ring structures

J. Sparso, J. Staunstrup, 1993, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences.

Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip

T. Bjerregaard, J. Sparso, 2004, Proceedings Norchip Conference, 2004..

Custom topology generation for network-on-chip

J. Sparso, M.B. Stuart, 2007, Norchip 2007.

A heterogeneous multiprocessor architecture for low-power audio signal processing applications

O. Paker, J. Sparso, N. Haandbaek, 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

A 85 /spl mu/W asynchronous filter-bank for a digital hearing aid

J. Sparso, F. Nielsen, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

Analytical derivation of traffic patterns in shared memory architectures from Task Graphs

J. Sparso, M.B. Stuart, 2009, 2009 NORCHIP.

IR-drop reduction in sub-VT circuits by de-synchronization

A. Karlsson, J. N. Rodrigues, J. Sparso, 2012, 2012 IEEE Subthreshold Microelectronics Conference (SubVT).

Asynchronous design of networks-on-chip

J. Sparso, J. Sparsø, 2007, Norchip 2007.