Chao-Yang Yeh

Clock distribution architectures: a comparative study

Rajeev Murgai, William W. Walker, Hongyu Chen, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC

H. Mair, V. Lin, G. Gammie, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC).

Timing-Aware Power-Noise Reduction in Placement

Malgorzata Marek-Sadowska, Chao-Yang Yeh, M. Marek-Sadowska, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Skew-programmable clock design for FPGA and skew-aware placement

Malgorzata Marek-Sadowska, Chao-Yang Yeh, M. Marek-Sadowska, 2005, FPGA '05.

Sequential delay budgeting with interconnect prediction

Malgorzata Marek-Sadowska, Chao-Yang Yeh, M. Marek-Sadowska, 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.