Young-Chan Jang

发表

A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface

Pil-Ho Lee, Young-Chan Jang, 2019, IEEE Transactions on Consumer Electronics.

A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination

Young-Chan Jang, 2010, IEICE Trans. Electron..

Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk

Young-Chan Jang, Hyun Bae Lee, 2012, IEICE Trans. Electron..

A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators

Pil-Ho Lee, Young-Chan Jang, Sang-Min Park, 2016, IEICE Trans. Electron..

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis

Pil-Ho Lee, Young-Chan Jang, Hyun Bae Lee, 2016, IEICE Trans. Electron..

1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit

Young-Chan Jang, Sang-Hun Kim, Han-Yeol Lee, 2012 .

A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver

Pil-Ho Lee, Young-Chan Jang, Jin-Woo Park, 2017, 2017 International SoC Design Conference (ISOCC).

A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY

Pil-Ho Lee, Young-Chan Jang, Jin-Wook Han, 2020 .

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock

Pil-Ho Lee, Young-Chan Jang, Han-Yeol Lee, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An 8-Bit 100-kS/s CMOS Single-Ended SA ADC for 8×8 Point EEG/MEG Acquisition System

Young-Chan Jang, Yeon-Ho Jeong, Ji-Hun Eo, 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 10-bit 20-MS/s asynchronous SAR ADC with controllable analog input voltage range and meta-stability detection circuit

Pil-Ho Lee, Young-Chan Jang, Sang-Min Park, 2014, 2014 International SoC Design Conference (ISOCC).

A 10 Gbps D-PHY Transmitter Bridge Chip for FPGA-Based Frame Generator Supporting MIPI DSI of Mobile Display

Pil-Ho Lee, Young-Chan Jang, Seung-Hun Shin, 2017, IEICE Trans. Electron..

An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter

Hong-June Park, Young-Chan Jang, Sang-Hune Park, 2003 .

CMOS digital duty cycle correction circuit for multi-phase clock

Hong-June Park, Young-Chan Jang, Seung-Jun Bae, 2003 .

A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization

Pil-Ho Lee, Young-Chan Jang, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 125 MHz CMOS Delay-Locked Loop with 32-phase Output Clock

Young-Chan Jang, Kwang-Hun Lee, 2013 .

A Time-Domain Comparator for Micro-Powered Successive Approximation ADC

Young-Chan Jang, Sang-Hun Kim, Ji-Hun Eo, 2012 .

A 10-bit CMOS Digital-to-Analog Converter with Compact Size for Display Applications

Young-Chan Jang, Hoon-Ju Chung, Mungyu Kim, 2014, IEICE Trans. Electron..

A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2

Pil-Ho Lee, Young-Chan Jang, Yeong-Woong Kim, 2017, IEEE Transactions on Consumer Electronics.

A 1.8 V 40-MS/sec 10-bit 0.18-㎛ CMOS Pipelined ADC using a Bootstrapped Switch with Constant Resistance

Sang-Hun Kim, Young-Chan Jang, Mungyu Kim, 2012, J. Inform. and Commun. Convergence Engineering.

BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel

Jung Sunwoo, Young-Chan Jang, Yun-Sang Lee, 2009, IEEE Journal of Solid-State Circuits.

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle

Pil-Ho Lee, Young-Chan Jang, Hyun Bae Lee, 2014, IEICE Trans. Electron..

Cascaded voting process for flash ADC with interpolating scheme

Young-Chan Jang, 2008 .

A 3Gbps/Lane MIPI D-PHY Transmission Buffer Chip

Pil-Ho Lee, Young-Chan Jang, 2019, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Self-Calibrating Per-Pin Phase Adjuster for Source Synchronous Double Data Rate Signaling in Parallel Interface

Young-Chan Jang, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 1.8 V 0.18-μm 1 GHz CMOS Fast-Lock Phase-Locked Loop using a Frequency-to-Digital Converter

Young-Chan Jang, Kwang-Hun Lee, 2012, J. Inform. and Commun. Convergence Engineering.

An unmatched source synchronous I/O link for jitter reduction in a multi-phase clock system

Young-Chan Jang, 2010, IEICE Electron. Express.

A true single-phase clocked flip-flop with leakage current compensation

Young-Chan Jang, Han-Yeol Lee, 2012, IEICE Electron. Express.

0.5 kHz–32 MHz digital fractional-N frequency synthesizer with burst-frequency switch

Pil-Ho Lee, Young-Chan Jang, Jin-Woo Park, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A digital phase corrector with a duty cycle detector and transmitter for a Quad Data Rate I/O scheme

Young-Chan Jang, 2010, IEICE Electron. Express.

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

Kee-Won Kwon, Jung Sunwoo, Jin-Young Kim, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A Threshold-voltage Sensing Circuit using Single-ended SAR ADC for AMOLED Pixel

Young-Chan Jang, Jisu Son, 2020 .

6-Gbps Single-ended Receiver with Continuous-time Linear Equalizer and Self-reference Generator

Pil-Ho Lee, Young-Chan Jang, 2016 .

A 10-bit 100-kS/s Successive Approximation Register ADC with improved Split Capacitor-based DAC

Young-Chan Jang, Yeon-Ho Jeong, 2013 .

Gain-Scheduled Control for an Active Suspension System with an Asymetric Hydraulic Actuator

Young-Chan Jang, 2002 .

A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface

Sang-Hun Kim, Young-Chan Jang, Ji-Hun Eo, 2011, IEICE Trans. Electron..

A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor

Young-Chan Jang, Yeon-Ho Jeong, 2014 .

A 10-bit 20-MS/s Asynchronous SAR ADC using Self-calibrating CDAC

Young-Chan Jang, Eunji Youn, 2019 .

An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator

Jae-Yoon Sim, Hong-June Park, Young-Chan Jang, 2007, IEICE Trans. Electron..

A Bootstrapped Analog Switch with Constant On-Resistance

Yong-Hwan Lee, Sang-Hun Kim, Young-Chan Jang, 2011, IEICE Trans. Electron..

121.15MHz Frequency Synthesizers using Multi-phase DLL-based Phase Selector and Fractional-N PLL

Pil-Ho Lee, Young-Chan Jang, Seung-Yong Lee, 2013 .

Erratum: A Swing Level Controlled Transmitter for Single-Ended Signaling with Center-Tapped Termination [IEICE Transactions on Electronics E93.C (2010) , No. 6 pp.861-863]

Young-Chan Jang, 2010 .

A 10-bit 10-MS/s single-ended asynchronous SAR ADC with CDAC boosting common-mode voltage and controlling input voltage range

Young-Chan Jang, Jisu Son, 2019, IEICE Electron. Express.

A 1.2 V 7-bit 1 GS/s CMOS Flash ADC with Cascaded Voting and Offset Calibration

Jae-Yoon Sim, Hong-June Park, Young-Chan Jang, 2008 .

12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration

Young-Chan Jang, Eunji Youn, 2018, 2018 International SoC Design Conference (ISOCC).

A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC

Young-Chan Jang, Yeon-Ho Jeong, 2013 .

A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces

Young-Chan Jang, Kwang-Hun Lee, 2014, IEICE Trans. Electron..

A 1.88-mW/Gb/s 5-Gb/s Transmitter with Digital Impedance Calibration and Equalizer

Young-Chan Jang, Ho-Seong Kim, Seung-Wuk Beak, 2016 .

A 10-bit 100-MS/s Pipelined SAR ADC with Redundancy Generation using Capacitor-based DAC and Linearity-improved Dynamic Amplifier

Young-Chan Jang, Han-Yeol Lee, Eunji Youn, 2019 .

CMOS sense amplifier-based flip-flop with two N-C/sup 2/MOS output latches

Hong-June Park, Young-Chan Jang, Jin-Cheon Kim, 2000 .

A mixed-mode single-chip motor-drive-specific microcontroller with a 12-bit 125/KS/s ADC

Hong-June Park, Young-Chan Jang, Jin-Cheon Kim, 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control

Hong-June Park, Young-Chan Jang, Jun-Hyun Bae, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

31.3: A 10‐bit CMOS Digital‐to‐Analog Converter with Logarithmic Time Interpolation

Young-Chan Jang, Hoon-Ju Chung, Mungyu Kim, 2013 .

An 8-GS/s 4-Bit 340 mW CMOS time interleaved flash analog to digital converter

Young-Chan Jang, 2004 .