E. R. Hsieh

发表

The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond

H. W. Chen, E. R. Hsieh, Steve S. Chung, 2019, 2019 Symposium on VLSI Circuits.

First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability

J. L. Kuo, E. R. Hsieh, Steve S. Chung, 2017, 2017 Symposium on VLSI Technology.

The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found

E. R. Hsieh, S. S. Chung, C. H. Tsai, 2012, 2012 International Electron Devices Meeting.

The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown

E. R. Hsieh, Steve S. Chung, C. T. Tsai, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring high speed, ultra-low power, and low voltage operation

E. R. Hsieh, Steve S. Chung, C. H. Chuang, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A novel one transistor non-volatile memory feasible for NOR and NAND applications in IoT era

E. R. Hsieh, Steve S. Chung, C. H. Chuang, 2016, 2016 IEEE Silicon Nanoelectronics Workshop (SNW).

A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory

E. R. Hsieh, Steve S. Chung, S. P. Yang, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

The issues on the power consumption of trigate FinFET: The design and manufacturing guidelines

E. R. Hsieh, Steve S. Chung, 2017, 2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).

A comprehensive transport model for high performance HEMTs considering the parasitic resistance and capacitance effects

E. R. Hsieh, Steve S. Chung, K. C. Li, 2014, 2014 Silicon Nanoelectronics Workshop (SNW).

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Steve S. Chung, C. H. Chien, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology

E. R. Hsieh, Steve S. Chung, R. M. Huang, 2014, 2014 IEEE International Electron Devices Meeting.

A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications

E. R. Hsieh, Steve S. Chung, C. H. Liu, 2018, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path

E. R. Hsieh, Steve S. Chung, W. Y. Yang, 2021, 2021 IEEE International Reliability Physics Symposium (IRPS).

The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique

E. R. Hsieh, S. S. Chung, C. Tsai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors

E. R. Hsieh, Steve S. Chung, 2010 .

New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress

E. R. Hsieh, Steve S. Chung, C. Tsai, 2011, 2011 International Reliability Physics Symposium.

Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications

E. R. Hsieh, Steve S. Chung, C. H. Chien, 2015, 2015 Silicon Nanoelectronics Workshop (SNW).

A new type of inverter with Juctionless (J-Less) transistors

E. R. Hsieh, Steve S. Chung, 2010, 2010 Silicon Nanoelectronics Workshop.

New Observations on the Corner Effect and STI-Induced Effect in Trigate CMOS Devices

E. R. Hsieh, Steve S. Chung, C. H. Tsai, 2013 .

The understanding of strain-induced device degradation in advanced MOSFETs with process-induced strain technology of 65nm node and beyond

E. R. Hsieh, Steve S. Chung, Y. H. Lin, 2010, 2010 IEEE International Reliability Physics Symposium.