Philip Pan

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface

J. Tyhach, B. Wang, C. Sung, 2005, IEEE Journal of Solid-State Circuits.

Architectural enhancements in Stratix-III™ and Stratix-IV™

David M. Lewis, Tim Vanderhoek, Andy Lee, 2009, FPGA '09.