S. Nakazawa

Transient analysis of a spatial power combining amplifier

C.E. Christoffersen, S. Nakazawa, M.A. Summers, 1999, 1999 IEEE MTT-S International Microwave Symposium Digest (Cat. No.99CH36282).

256 Mbit synchronous DRAM

S. Nakazawa, Kyoichi Nagata, Tatsuya Matano, 1997 .

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Y. Takai, S. Nakazawa, Y. Kobayashi, 2000, IEEE Journal of Solid-State Circuits.

A 600 MHz single-chip multiprocessor with 4.8 GB/s internal shared pipelined bus and 512 kB internal memory

N. Okumura, M. Nakajima, H. Kondo, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

Integrated electromagnetic and circuit modeling of large microwave and millimeter-wave structures

S. Nakazawa, M.B. Steer, J. Harvey, 1998, IEEE Antennas and Propagation Society International Symposium. 1998 Digest. Antennas: Gateways to the Global Network. Held in conjunction with: USNC/URSI National Radio Science Meeting (Cat. No.98CH36.

An integrated electromagnetic and nonlinear circuit simulation environment for spatial power combining systems

S. Nakazawa, M.B. Steer, J.W. Mink, 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).