Longbing Zhang

EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model

Limin Xiao, Rui Liu, Mingfa Zhu, 2017, Frontiers of Computer Science.

Address-Locking Cache: A Flexible on Chip Memory Implementation for Embedded System

Jing Wang, Wen Su, Longbing Zhang, 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread

Hou Rui, Weiwu Hu, Longbing Zhang, 2007, Microprocess. Microsystems.

A Fault-Tolerant Java Virtual Machine Using Fast Rejuvenation for Soft-Error-Prone Systems

Bin Liao, Jie Fu, Shuai Chen, 2015, 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conference on Embedded Software and Systems.

An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits

Limin Xiao, Rong Zhang, Fei Gu, 2016, Frontiers of Computer Science.

Efficiency-Aware QoS DRAM Scheduler

Qi Liu, Xiang Gao, Yunji Chen, 2009, 2009 IEEE International Conference on Networking, Architecture, and Storage.

Processes Scheduling on Heterogeneous Multi-core Architecture with Hardware Support

Jian Wang, Qi Liu, Longbing Zhang, 2011, 2011 IEEE Sixth International Conference on Networking, Architecture, and Storage.

Using Direct Cache Access Combined with Integrated NIC Architecture to Accelerate Network Processing

Xiang Gao, Dan Tang, Wen Su, 2012, 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems.

An Efficient Polarity Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Novel Binary Differential Evolution Algorithm

Limin Xiao, Shaobo Liu, Fei Gu, 2017, NPC.

MRP: Mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation

Peng Wu, Guangfei Zhang, Huandong Wang, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Parallel program performance evaluation and their behavior analysis on an OpenMP cluster

Fei Cai, Longbing Zhang, Shaogang Wu, 2004, IEEE International Symposium on Cluster Computing and the Grid, 2004. CCGrid 2004..

A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors

Hou Rui, Weiwu Hu, Longbing Zhang, 2006, Euro-Par.

EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions

Limin Xiao, Rui Liu, Mingfa Zhu, 2016, 2016 International Conference on Field-Programmable Technology (FPT).

Stable Matching Scheduler for Single-ISA Heterogeneous Multi-core Processors

Chao Lu, Jian Wang, Lei Wang, 2015, APPT.

Archipelago: A Floorplan Optimized for Concurrent Multiple Applications on Network-on-Chip

Chao Lu, Lei Wang, Shaoli Liu, 2014, 2014 9th IEEE International Conference on Networking, Architecture, and Storage.

CAOS: combined analysis with online sifting for dynamic compilation systems

Jian Wang, Jie Fu, Guojie Jin, 2016, Conf. Computing Frontiers.

A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions

Limin Xiao, Rui Liu, Mingfa Zhu, 2017, Journal of Computer Science and Technology.