Mateusz Kuc

Hardware implementation of the LDPC decoder in the FPGA structure

Dariusz Kania, Wojciech Sulek, Mateusz Kuc, 2021 .

Low Power QC-LDPC Decoder Based on Token Ring Architecture

Dariusz Kania, Mateusz Kuc, Wojciech Sulek, 2020, Energies.

FPGA-Oriented LDPC Decoder for Cyber-Physical Systems

Dariusz Kania, Mateusz Kuc, Wojciech Sulek, 2020, Mathematics.