N. Chauvet

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

C. Fenouillet-Béranger, R. Beneyton, J. Mazurier, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Atomic layer etching of GaN using Cl2 and He or Ar plasma

N. Possémé, P. Pimenta-Barros, Frédéric Roux, 2021 .