Chih-Yu Lin

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Hidehiro Fujiwara, Po-Yi Huang, Jonathan Chang, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications

Hidehiro Fujiwara, Jonathan Chang, Hung-Jen Liao, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).